Granted Patent B2

US 11,126,583 · App. 16/921,923 · Granted Sep 21, 2021

Inventors: Sompong Paul Olarig (Pleasanton, CA); Son T. Pham (San Ramon, CA); Fred Worley (San Jose, CA)

G06F13/4234G06F13/387G06F13/4282G06F2213/0026

Abstract

Claims (39)

1. A device, comprising:

a connector to connect the device to a component in a chassis;

first circuitry to determine a type of the chassis including the device; and

second circuitry to configure the device to use a first mode or a second mode responsive to the type of the chassis,

wherein the first mode includes a first transport protocol to communicate between the device and the chassis,

wherein the second mode includes a second transport protocol to communicate between the device and the chassis, and

wherein the component performs a function in addition to determining a type of the chassis including the device.

2. The device according to claim 1 , wherein the first circuitry is operative to determine the type of the chassis from a signal on a pin on the connector.

3. The device according to claim 1 , wherein the first circuitry is operative to determine the type of the chassis including the device from the component.

4. The device according to claim 1 , wherein the first circuitry is operative to read the type of the chassis from a Vital Product Data (VPD).

5. The device according to claim 1 , wherein the connector supports a plurality of Peripheral Component Interconnect Express (PCIe) lanes and Serial Attached Small Computer System Interface (SCSI) (SAS) pins.

6. The device according to claim 5 , wherein, based at least in part on the type of the chassis being Non-Volatile Memory Express (NVMe), the second circuitry is operative to use two lanes of the PCIe lanes as both a data plane and a control plane for a host and to disable use of an Ethernet port via the SAS pins.

7. The device according to claim 5 , wherein, based at least in part on the type of the chassis being Non-Volatile Memory Express over Fabric (NVMeoF), the second circuitry is operative to use two lanes of the PCIe lanes as a control plane for a host, and to use a set of SAS pins as an Ethernet port for a data plane for the host.

8. A method, comprising:

determining a type of chassis in which a device is installed, where the device is coupled to a component in the chassis using a connector, the component performing a function in addition to determining a type of the chassis including the device; and

configuring the device to enable a first communication mechanism and disable a second communication mechanism for the device according to the type of the chassis.

9. The method according to claim 8 , wherein determining a type of chassis in which a device is installed includes accessing a signal from a pin on the connector.

10. The method according to claim 8 , wherein

determining a type of chassis in which a device is installed includes determining the type of the chassis from the component.

11. The method according to claim 8 , wherein determining a type of chassis in which a device is installed includes reading the type of the chassis from a Vital Product Data (VPD).

12. The method according to claim 8 , wherein configuring the device to enable a first communication mechanism and disable a second communication mechanism for the device according to the type of the chassis includes, based at least in part on the type of the chassis being a Non-Volatile Memory Express (NVMe) chassis:

enabling two lanes in a Peripheral Component Interconnect Express (PCIe) bus as both a data plane and a control plane for a host; and

disabling an Ethernet port for the host.

13. The method according to claim 8 , wherein configuring the device to enable a first communication mechanism and disable a second communication mechanism for the device according to the type of the chassis includes, based at least in part on the type of the chassis being a Non-Volatile Memory Express over Fabric (NVMeoF) chassis:

enabling two lanes in a PCIe bus as a control plane for a host; and

enabling an Ethernet port as a data plane for the host using a pair of SAS pins on the connector as the Ethernet port.

14. An article, comprising a tangible non-transitory storage medium, the tangible non-transitory storage medium having stored thereon non-transitory instructions that, when executed by a machine, result in:

determining a type of chassis in which a device is installed, where the device is coupled to a component in the chassis using a connector, the component performing a function in addition to determining a type of the chassis including the device; and

configuring the device to enable a first communication mechanism and disable a second communication mechanism for the device according to the type of the chassis.

15. The article according to claim 14 , wherein determining a type of chassis in which a device is installed includes accessing a signal from a pin on the connector.

16. The article according to claim 14 , wherein

determining a type of chassis in which a device is installed includes determining the type of the chassis from the component.

17. The article according to claim 14 , wherein determining a type of chassis in which a device is installed includes reading the type of the chassis from a Vital Product Data (VPD).

18. The article according to claim 14 , wherein configuring the device to enable a first communication mechanism and disable a second communication mechanism for the device according to the type of the chassis includes, based at least in part on the type of the chassis being a Non-Volatile Memory Express (NVMe) chassis:

enabling two lanes in a Peripheral Component Interconnect Express (PCIe) bus as both a data plane and a control plane for a host; and

disabling an Ethernet port for the host.

19. The article according to claim 14 , wherein configuring the device to enable a first communication mechanism and disable a second communication mechanism for the device according to the type of the chassis includes, based at least in part on the type of the chassis being a Non-Volatile Memory Express over Fabric (NVMeoF) chassis:

enabling two lanes in a PCIe bus as a control plane for a host; and

enabling an Ethernet port as a data plane for the host using a pair of SAS pins on the connector as the Ethernet port.

Assignments (1)

Continuity (12)

Cited By (5)

US 12,541,477 US 12,541,480 US 12,556,417 US 12,561,266 US 12,561,270