Systems and methods for multi-bit memory with embedded logic
Systems and method are provided that include a standard cell with multiple input and output storage elements, such as flip flops, latches, etc., with some combination logic interconnected between them. In embodiments, the slave latches on input flip flops are replaced with a fewer number latches at a downstream node(s) of the combination logic resulting in improved performance, area and power, while maintaining functionality at the interface pins of the standard cell. The process of inferring such a standard cell from a behavioral description, such as RTL, of a design or remapping equivalent sub-circuits from a netlist to such a standard cell is also described.
1. A method for optimizing a design, comprising:
accessing a model of the design;
using the model to identify a replaceable segment of the design, based on an identification of multibit first storage followed by a logic function followed by second storage;
modifying the design by automatically replacing the components of the replaceable segment with a standard cell that comprises:
a plurality of input stage master latches;
a function that replicates operation of the logic function that receives output from the plurality of input stage master latches;
a slave latch that receives output from the logic function; and
an output storage element that receives output from the slave latch; and
storing the modified design in a non-transitory computer-readable medium.
2. The method of claim 1 , wherein the model of the design comprises a register transfer-level specification of the design.
3. The method of claim 1 , wherein the model of the design comprises a netlist.
4. The method of claim 1 , further comprising synthesizing an integrated circuit, wherein the synthesizing comprises:
routing an input signal for each input stage master latch from upstream cells to the standard cell; and
routing an output signal from the output storage element to a downstream cell.
5. The method of claim 4 , wherein the synthesizing does not include routing signals within the replaceable segment from a multibit flip flop to the logic function and further does not include routing signals within the replaceable segment from the logic function to the second storage.
6. The method of claim 1 , wherein the replaceable segment comprises a plurality of standard cells, wherein said replacing reduces a total number of standard cells of the design.
7. The method of claim 1 , wherein the replaceable segment does not include pass transistor logic, and wherein the standard cell include the pass transistor logic.
8. A method of automating design of an integrated circuit, comprising:
receiving an integrated circuit design file that specifies a plurality of multi-stage data storage elements;
identifying one or more logic functions positioned between a first data storage element and a second data storage element;
automatically modifying the integrated circuit design by:
deleting a second stage of the first data storage element in the integrated circuit design;
routing a first stage of the first data storage element to the one or more logic functions; and
routing output of the one or more logic functions to a second stage that is further routed to the second data storage element; and
storing the modified integrated circuit design in a non-transitory computer-readable medium.
9. The method of claim 8 , wherein a physical integrated circuit is fabricated based on the modified integrated circuit design.
10. The method of claim 8 , wherein the first data storage element is a flip flop.
11. The method of claim 8 , wherein the first stage of the flip flop is a master stage, and wherein the second stage of the flip flop is a slave stage.
12. The method of claim 8 , wherein the one or more logic functions are positioned between multiple first data storage elements and a second data storage element;
wherein the automatically modifying comprises:
deleting second stages of each of the first data storage elements;
routing first stages of the first data storage elements to the one or more logic functions;
wherein routing output of the one or more logic functions to the single second stage that is further routed to the second data storage element.
13. The method of claim 12 , wherein the one or more logic functions comprise a multiplexer, wherein the received integrated circuit design specifies the multiple first data storage elements as providing input to the multiplexer, and wherein the multiplexer output is provided to the second data storage element.
14. The method of claim 8 , wherein the modified integrated circuit design includes (n−1) fewer second stages, wherein n is equal to a count of the multiple first data storage elements.
15. The method of claim 8 , wherein the second data storage element is a flip flop comprising a master stage and a slave stage, wherein output of the second stage that receives the output of the one or more logic functions is routed to the master stage of the flip flop.
16. The method of claim 8 wherein timing signals are provided to the first stage, the second stage, and the second data storage element based on a clock signal.
17. The method of claim 8 , wherein the one or more logic functions are positioned between the first data storage element and multiple second data storage elements;
wherein outputs of the one or more logic functions are routed directly to second stages of the plurality of second data storage elements following removal of first stages of the plurality of second data storage elements.
18. The method of claim 17 , wherein the one or more logic functions includes a demultiplexer.
19. A computer-readable medium encoded with a cell library containing data associated with a plurality of standard cells for performing electronic design automation, the cell library comprising:
a standard cell data record, comprising:
a logic definition that includes:
a plurality of input stage master latches, each input stage master latch receiving a clock signal;
a logic function that receives output from the plurality of input stage master latches;
a slave latch that receives output from the logic function, the slave latch receiving a timing signal based on the clock signal; and
an output storage element that receives output from the slave latch;
a physical definition comprising identification of a plurality of transistors for implementing a cell associated with the standard cell data record and routing among the plurality of transistors; and
timing information associated with the standard cell, wherein the timing information is generated via simulation.
20. The computer-readable medium of claim 19 , wherein the output storage element is a flip flop that receives a second timing signal based on the clock signal.