Semiconductor device, method for manufacturing semiconductor device, and PID protection device
The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a plasma-induced damage (PID) protection device capable of, without increasing a chip area, releasing a large PID with high efficiency and protecting an element to be protected from the PID with higher accuracy. There are provided a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a MOSFET to be protected and a grounded source and protects the MOSFET to be protected from a plasma-induced damage (PID), and a dummy antenna connected to a gate electrode of the protection MOSFET, the dummy antenna turning on the protection MOSFET prior to the MOSFET to be protected due to PID charge. The present disclosure can be applied to a semiconductor device.
1. A semiconductor device, comprising:
a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a first MOSFET and a grounded source, wherein the protection MOSFET is configured to protect the first MOSFET from a plasma-induced damage (PID); and
a dummy antenna connected to a gate electrode of the protection MOSFET, wherein
the dummy antenna is configured to turn on the protection MOSFET before accumulation of charge in the gate electrode of the first MOSFET due to PID charge, and
the dummy antenna includes a via having a diameter smaller than a diameter of a via connected to the first MOSFET.
2. The semiconductor device according to claim 1 , wherein
the dummy antenna includes wiring that has a pitch smaller than a pitch of wiring connected to the first MOSFET.
3. The semiconductor device according to claim 1 , further comprising:
a potential switching unit configured to switch potential of the gate electrode of the protection MOSFET to ground potential based on in a case where the PID charge is not generated.
4. The semiconductor device according to claim 3 , wherein
the potential switching unit is a diode between the gate electrode and a substrate, and
a forward direction of the diode is directed to the substrate.
5. The semiconductor device according to claim 3 , wherein
the potential switching unit is a resistor between the gate electrode and a substrate.
6. The semiconductor device according to claim 3 , wherein
the potential switching unit is a second MOSFET between the gate electrode and a substrate.
7. A plasma-induced damage (PID) protection device, comprising:
a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a first MOSFET and a grounded source, wherein the protection MOSFET is configured to protect the MOSFET from a PID; and
a dummy antenna connected to a gate electrode of the protection MOSFET, wherein
the dummy antenna is configured to turn on the protection MOSFET before accumulation of charge in the gate electrode of the first MOSFET due to PID charge, and
the dummy antenna includes a via having a diameter smaller than a diameter of a via connected to the first MOSFET.
8. The PID protection device according to claim 7 , further comprising:
a potential switching unit configured to:
function as a resistor based on a flow of current from the gate electrode of the first MOSFET to a substrate through a channel of the protection MOSFET; and
function as a ground potential when the current does not flow.
9. The PID protection device according to claim 8 , wherein
the potential switching unit is a diode between the gate electrode and the substrate, and
a forward direction of the diode is directed to the substrate.
10. The PID protection device according to claim 8 , wherein
the potential switching unit is the resistor between the gate electrode and the substrate.
11. The PID protection device according to claim 8 , wherein
the potential switching unit is a second MOSFET between the gate electrode and the substrate.