Multi-threshold gate structure with doped gate dielectric layer
The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.
1. A method, comprising:
depositing a first gate dielectric material on a plurality of nanowires, the plurality of nanowires formed in first and second device regions;
forming a first dopant layer on the first gate dielectric material in the first device region;
forming a second dopant layer on the first dopant layer in the first device region and on the first gate dielectric material in the second device region;
performing an anneal process on the first gate dielectric material and on the first and second dopant layers;
removing the first and second dopant layers;
depositing a second gate dielectric material on the first gate dielectric material;
forming a first work function layer on the second gate dielectric material;
forming a second work function layer on the first work function layer; and
forming gate electrodes on the second work function layer.
2. The method of claim 1 , wherein depositing the first and second gate dielectric materials comprises depositing hafnium oxide.
3. The method of claim 1 , wherein forming the first and second dopant layers comprises depositing lanthanum oxide.
4. The method of claim 1 , wherein performing the anneal process comprises rapid thermal annealing (RTA) the first gate dielectric material and the first and second dopant layers at a temperature between about 600° C. and about 800° C.
5. The method of claim 1 , further comprising performing a plasma treatment process on the first work function layer with titanium chloride and silane as precursors.
6. A method, comprising:
depositing a gate dielectric layer on first and second pluralities of semiconductor layers;
depositing a first dopant layer around each semiconductor layer of the first and second pluralities of semiconductor layers;
removing portions of the first dopant layer deposited around the second plurality of semiconductor layers;
depositing a second dopant layer on remaining portions of the first dopant layer and around each semiconductor layer of the second plurality of semiconductor layers; and
performing an anneal process on the gate dielectric layer, the remaining portions of the first dopant layer, and the second dopant layer.
7. The method of claim 6 , further comprising:
removing the remaining portions of the first dopant layer; and
removing the second dopant layer.
8. The method of claim 7 , further comprising depositing first and second work function layers over the first and second pluralities of semiconductor layers, respectively.
9. The method of claim 8 , wherein depositing the first and second work function layers comprises depositing n-type and p-type materials, respectively.
10. The method of claim 8 , wherein depositing the first and second work function layers comprises depositing p-type and n-type materials, respectively.
11. The method of claim 8 , further comprising performing a plasma treatment process on the first work function layer using titanium chloride and silane as precursors.
12. The method of claim 6 , wherein depositing the gate dielectric layer comprises depositing hafnium oxide.
13. The method of claim 6 , wherein depositing the first and second dopant layers comprises depositing lanthanum oxide.
14. The method of claim 6 , wherein performing the anneal process comprises performing a rapid thermal annealing (RTA) process at a temperature between about 600° C. and about 800° C.
15. The method of claim 6 , further comprising depositing an other gate dielectric layer on the gate dielectric layer.
16. A method, comprising:
forming a first gate dielectric layer with a first atomic dopant ratio, comprising:
depositing an intrinsic gate dielectric material;
depositing first and second dopant layers on a first portion of the intrinsic gate dielectric material; and
performing an anneal process on the first portion of the intrinsic gate dielectric material and the first and second dopant layers; and
forming a second gate dielectric layer having a second atomic dopant ratio lower than the first atomic dopant ratio, comprising:
depositing the second dopant layer on a second portion of the intrinsic gate dielectric material; and
performing the anneal process on the second portion of the intrinsic gate dielectric material and the second dopant layer.
17. The method of claim 16 , wherein depositing the intrinsic gate dielectric material comprises depositing hafnium oxide.
18. The method of claim 16 , wherein depositing the first and second dopant layers comprises depositing lanthanum oxide.
19. The method of claim 16 , wherein performing the anneal process comprises performing a rapid thermal annealing (RTA) process at a temperature between about 600° C. and about 800° C.
20. The method of claim 16 , further comprising removing the first and second dopant layers after performing the anneal process.