Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors

1. A transistor comprising:

semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem, the semiconductor material of the stem comprising an upper source/drain region and a channel region there-below;

only (a) of (a) and (b), where

(a): the semiconductor material of the stem comprises a lower source/drain region below the channel region; and

(b): the semiconductor material of the base comprises a lower source/drain region; and

a gate operatively laterally adjacent the channel region of the stem;

said transistor being part of an array of said transistors wherein individual of said gates are an individual portion of individual wordlines that interconnect individual of the transistors along that individual wordline; and

comprising individual pairs of immediately-laterally-adjacent transistors, one individual of the semiconductor material within each pair of the immediately-laterally-adjacent transistors being generally L-shaped in the at least one straight-line vertical cross-section, the other individual semiconductor material within each pair of the immediately-laterally-adjacent transistors being generally mirror L-shaped in the at least one straight-line vertical cross-section.

2. An array of transistors, comprising:

transistors individually comprising:

semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem, the semiconductor material of the stem comprising an upper source/drain region and a channel region there-below;

at least one of (a) and (b), where

(a): the semiconductor material of the stem comprises a lower source/drain region below the channel region; and

(b): the semiconductor material of the base comprises a lower source/drain region;

a gate operatively laterally adjacent the channel region of the stem;

individual of said gates are an individual portion of individual wordlines that interconnect individual of the transistors along that individual wordline;

individual pairs of immediately-laterally-adjacent transistors, one individual of the semiconductor material within each pair of the immediately-laterally-adjacent transistors being generally L-shaped in the at least one straight-line vertical cross-section, the other individual semiconductor material within each pair of the immediately-laterally-adjacent transistors being generally mirror L-shaped in the at least one straight-line vertical cross-section;

the pairs of the immediately-laterally-adjacent transistors are further laterally apart from one another than are individual of the transistors within each pair of the immediately-laterally-adjacent transistors; and

the bases of the respective immediately-laterally-adjacent transistors in the pairs extending horizontally toward one another from their respective stem.

3. The transistors of the array of claim 2 comprising (a).

4. The transistors of the array of claim 3 comprising only (a) of (a) and (b).

5. The transistors of the array of claim 2 comprising (b).

6. The transistors of the array of claim 5 comprising only (b) of (a) and (b).

7. The transistors of the array of claim 2 comprising (a) and (b).