Transistor having in-situ doped nanosheets with gradient doped channel regions

1. A method of performing fabrication operations to form a transistor, wherein the fabrication operations include:

forming a nanosheet comprising a first nanosheet sidewall and a second nanosheet sidewall;

communicatively coupling the nanosheet to a source region at the first nanosheet sidewall;

communicatively coupling the nanosheet to a drain region at the second nanosheet sidewall;

wherein the nanosheet further comprises a source-side nanosheet region that includes the first nanosheet sidewall;

wherein the nanosheet further comprises a drain-side nanosheet region that includes the second nanosheet sidewall; and

providing dopants in the source-side nanosheet region by using an in-situ doping process;

wherein a doping concentration in the source-side nanosheet region is greater than a doping concentration of the drain-side nanosheet region.

2. The method of claim 1 , wherein forming the source-side nanosheet region comprises:

forming an initial nanosheet structure; and

replacing a portion of the initial nanosheet structure with the source-side nanosheet region.

3. The method of claim 2 , wherein replacing the portion of the initial nanosheet region structure with the source-side nanosheet region comprises epitaxially growing the source-side nanosheet region from an exposed surface of the initial nanosheet structure.

4. The method of claim 3 , wherein the in-situ doping process is part of epitaxially growing the source-side nanosheet region from the exposed surface of the initial nanosheet structure.

5. The method of claim 2 further comprising, subsequent to the in-situ doping process, forming a source-side extension region by exposing the source-side nanosheet region to a first temperature that is sufficient to cause the dopants in the source-side nanosheet region to diffuse into the initial nanosheet structure.

6. The method of claim 1 , wherein:

a gate structure is over a portion of the nanosheet;

the portion of the nanosheet comprises a channel region of the transistor; and

the channel region comprises a channel region bottom surface that defines a channel length dimension of the channel region.

7. The method of claim 6 , wherein:

a first portion of the channel region bottom surface comprises a source-side channel region bottom surface; and

a length dimension of the source-side channel region bottoms surface comprises between about 20% and about 40% of the channel length dimension of the channel region.

8. A method of performing fabrication operations to form a nanosheet field effect transistor (FET) device, wherein the fabrication operations include:

forming a nanosheet comprising a first nanosheet sidewall and a second nanosheet sidewall;

communicatively coupling the nanosheet to a source region at the first nanosheet sidewall;

communicatively coupling the nanosheet to a drain region at the second nanosheet sidewall;

wherein the nanosheet further comprises a source-side nanosheet region that includes the first nanosheet sidewall;

wherein the nanosheet further comprises a drain-side nanosheet region that includes the second nanosheet sidewall; and

providing dopants in the source-side nanosheet region, wherein the providing dopants in the source-side nanosheet region comprises incorporating an in-situ doping process into a process used to form the source-side nanosheet region;

wherein a doping concentration in the source-side nanosheet region is greater than a doping concentration of the drain-side nanosheet region.

9. The method of claim 8 , wherein the process used to form the nanosheet region comprises:

forming an initial nanosheet structure; and

replacing a portion of the initial nanosheet structure with the source-side nanosheet region.

10. The method of claim 9 , wherein replacing the portion of the initial nanosheet structure with the source-side nanosheet region comprises epitaxially growing the source-side nanosheet region from an exposed surface of the initial nanosheet structure.

11. The method of claim 10 , wherein the in-situ doping process is part of epitaxially growing the source-side nanosheet region from the exposed surface of the initial nanosheet structure.

12. The method of claim 9 further comprising, subsequent to the in-situ doping process, forming a source-side extension region by exposing the source-side nanosheet region to a first temperature that is sufficient to cause the dopants in the source-side nanosheet region to diffuse into the initial nanosheet structure.

13. The method of claim 8 , wherein:

a gate structure is over a portion of the nanosheet;

the portion of the nanosheet comprises a channel region of the transistor; and

the channel region comprises a channel region bottom surface that defines a channel length dimension of the channel region.

14. The method of claim 13 , wherein:

a first portion of the channel region bottom surface comprises a source-side channel region bottom surface; and

a length dimension of the source-side channel region bottoms surface comprises between about 20% and about 40% of the channel length dimension of the channel region.

15. A transistor comprising:

a nanosheet comprising a first nanosheet sidewall and a second nanosheet sidewall;

wherein the nanosheet is communicatively coupled to a source region at the first nanosheet sidewall;

wherein the nanosheet is communicatively coupled to a drain region at the second nanosheet sidewall;

wherein the nanosheet further comprises a source-side nanosheet region that includes the first nanosheet sidewall;

wherein the nanosheet further comprises a drain-side nanosheet region that includes the second nanosheet sidewall;

wherein the source-side nanosheet region comprises in-situ dopants; and

wherein a doping concentration in the source-side nanosheet region is greater than a doping concentration of the drain-side nanosheet region.

16. The transistor of claim 15 , wherein the source-side nanosheet region comprises multiple epitaxial layers.

17. The transistor of claim 16 , wherein the nanosheet further comprises a source-side extension region communicatively coupled to the source-side nanosheet region.

18. The transistor of claim 15 , wherein:

a gate structure is over a portion of the nanosheet;

the portion of the nanosheet comprises a channel region of the transistor; and

the channel region comprises a channel region bottom surface that defines a channel length dimension of the channel region.

19. The transistor of claim 18 , wherein a first portion of the channel region bottom surface comprises a source-side channel region bottom surface.

20. The transistor of claim 19 , wherein a length dimension of the source-side channel region bottoms surface comprises between about 20% and about 40% of the channel length dimension of the channel region.