IP Library Granted Patent US 11,166,367
Granted Patent B2
US 11,166,367 · App. 17/070,167 · Granted Nov 2, 2021

Setting the impedance of signal traces of a circuit board using a reference trace

Inventors: Manhtien V. Phan (Morgan Hill, CA); Mau-Lin Chou (Milpitas, CA); Chih-Hao Lee (NewTaipei, TW)
Assignee: Super Micro Computer, Inc.
H05K1/0253H05K1/0298H05K2201/093
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Quick Facts
Patent No.
US 11,166,367
App. No.
17/070,167
Granted
Nov 2, 2021
Kind
B2
Abstract

A circuit board has an edge connector with signal traces. The signal traces are formed on a dielectric layer of the circuit board. A reference trace is formed within the dielectric layer or on another surface of the dielectric layer. Parameters of the reference trace are adjusted to set an impedance of a single-ended signal trace or a differential impedance of two adjacent signal traces.

Claims (11)

1. A circuit board comprising:

a dielectric layer;

an edge connector disposed on a first surface of the dielectric layer, the edge connector comprising a plurality of contact fingers, a first contact finger and a second contact finger of the plurality of contact fingers being adjacent and configured to carry a differential signal; and

a reference trace within the dielectric layer, the reference trace being disposed directly under and between the first and second contact fingers, wherein the reference trace sets a differential impedance of the first and second contact fingers.

2. The circuit board of claim 1 , wherein the differential impedance of the first and second contact fingers is set to about 85 ohms.

3. The circuit board of claim 1 , wherein the reference trace has a width that is narrower than a spanning distance between outer perimeters of the first and second contact fingers.

4. The circuit board of claim 1 , further comprising a notch on the edge connector.

5. The circuit board of claim 1 , wherein the reference trace comprises copper.

6. The circuit board of claim 1 , further comprising a reference plane disposed on a second surface of the dielectric layer.

7. The circuit board of claim 1 , wherein the reference trace has a longitudinal portion that is in parallel with lengths of the first and second contact fingers.

8. The circuit board of claim 7 , wherein the reference trace has a T-shape with another portion that is perpendicular to the longitudinal portion.

Assignments (1)
SECURITY INTEREST Recorded Jan 20, 2026
From: SUPER MICRO COMPUTER, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 074447/0643 →
Continuity (2)
Continuation 16750686 · Jan 23, 2020
Related Publication 20210235578A1 · Jul 29, 2021