Bitcell for data redundancy
The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the first memory element and a ground. The bit cell also includes a second memory element coupled to the write bit line, and a second write-access switch coupled between the second memory element and the ground. The bit cell further includes a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line.
1. A bit cell, comprising:
a first memory element coupled to a write bit line;
a first write-access switch coupled between the first memory element and a ground;
a second memory element coupled to the write bit line;
a second write-access switch coupled between the second memory element and the ground; and
a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line, wherein a size of the first write-access switch is at least twice a size of the read-access switch.
2. The bit cell of claim 1 , wherein the first memory element comprises a first fuse and the second memory element comprises a second fuse.
3. The bit cell of claim 1 , wherein the bit cell is integrated in a memory array comprising multiple bit cells.
4. The bit cell of claim 1 , wherein a control input of the first write-access switch is coupled to a first write-select line, and a control input of the second write-access switch is coupled to a second write-select line.
5. A memory device, comprising:
a first bit cell, wherein the first bit cell comprises:
a first memory element coupled to a write bit line;
a first write-access switch coupled between the first memory element and a ground;
a second memory element coupled to the write bit line;
a second write-access switch coupled between the second memory element and the ground; and
a first read-access switch coupled between the first memory element and a read bit line, wherein a control input of the first read-access switch is coupled to a first read-select line, wherein a size of the first write-access switch is at least twice a size of the read-access switch; and
a sense amplifier coupled to the read bit line.
6. The memory device of claim 5 , further comprising a comparator coupled to the sense amplifier.
7. The memory device of claim 6 , wherein the comparator comprises a voltage-latched sense amplifier.
8. The memory device of claim 5 , wherein the sense amplifier comprises a current sense amplifier.
9. The memory device of claim 5 , further comprising a write driver coupled to the write bit line.
10. The memory device of claim 5 , wherein the first memory element comprises a first fuse and the second memory element comprises a second fuse.
11. The memory device of claim 5 , wherein a control input of the first write-access switch is coupled to a first write-select line, and a control input of the second write access switch is coupled to a second write-select line.
12. The memory device of claim 11 , further comprising a select circuit coupled to the first write-select line, the second write-select line, and the first read-select line.
13. The memory device of claim 5 , further comprising a second bit cell, wherein the second bit cell comprises:
a third memory element coupled to the write bit line;
a third write-access switch coupled between the third memory element and the ground;
a fourth memory element coupled to the write bit line;
a fourth write-access switch coupled between the fourth memory element and the ground; and
a second read-access switch coupled between the third memory element and the read bit line, wherein a control input of the second read-access switch is coupled to a second read-select line.
14. The memory device of claim 13 , wherein a control input of the first write-access switch is coupled to a first write-select line, a control input of the second write access switch is coupled to a second write-select line, a control input of the third write-access switch is coupled to a third write-select line, and a control input of the fourth write-access switch is coupled to a fourth write-select line.
15. The memory device of claim 14 , further comprising a select circuit coupled to the first write-select line, the second write-select line, the third write-select line, the fourth write-select line, the first read-select line, and the second read-select line.
16. A system, comprising:
a first memory device, wherein the first memory device comprises:
a bit cell, wherein the bit cell comprises:
a first memory element coupled to a write bit line;
a first write-access switch coupled between the first memory element and a ground;
a second memory element coupled to the write bit line;
a second write-access switch coupled between the second memory element and the ground; and
a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line, wherein a size of the first write-access switch is at least twice a size of the read-access switch; and
a read circuit coupled to the read bit line; and
a processor coupled to the read circuit.
17. The system of claim 16 , further comprising a register coupled to the processor.
18. The system of claim 16 , further comprising a second memory device coupled to the processor.
19. The system of claim 18 , wherein the second memory device comprises a read-only memory (ROM), a flash memory, a hard drive, or a solid state drive.
20. The system of claim 16 , wherein the first memory element comprises a first fuse and the second memory element comprises a second fuse.