Readout circuit for pixel
A readout circuit is provided. The readout circuit is coupled to a pixel circuit for reading out signals from the pixel circuit. The readout circuit includes a biasing circuit. The biasing circuit includes a cascode transistor and a biasing transistor. A first terminal of the cascode transistor is coupled to an output terminal of the biasing circuit and the pixel circuit. A second terminal of the cascode transistor is coupled to a first terminal of the biasing transistor. A second terminal of the biasing transistor is coupled to a negative voltage.
1. A readout circuit for reading out signals from a pixel circuit, comprising:
a biasing circuit, comprising a cascode transistor and a biasing transistor,
wherein a first terminal of the cascode transistor is coupled to an output terminal of the biasing circuit and the pixel circuit, a second terminal of the cascode transistor is coupled to a first terminal of the biasing transistor, and a second terminal of the biasing transistor is coupled to a negative voltage,
wherein the pixel circuit further comprises:
a reset transistor, wherein a first terminal of the reset transistor is coupled to a supply voltage, and a second terminal of the reset transistor is coupled to a floating diffusion node;
a photo diode, wherein a first terminal of the photo diode is coupled to the floating diffusion node, and a second terminal of the photo diode is coupled to a bias voltage;
a source follower transistor, wherein a first terminal of the source follower transistor is coupled to the supply voltage, and a control terminal of the source follower transistor is coupled to the floating diffusion node; and
a select transistor, wherein a first terminal of the select transistor is coupled to a second terminal of the source follower transistor, and a second terminal of the select transistor is coupled to the first terminal of the cascode transistor,
wherein the negative voltage meets a first equation: V_MINUS≤bias-2×V_OV-V_GS, wherein the symbol V_MINUS is represented the negative voltage, the symbol V_bias is represented a bias voltage received by a control terminal of the biasing transistor, the symbol 2*V_OV is represented two overdrive voltages of the biasing transistor and the cascode transistor, and the symbol V_GS is represented a gate-source voltage of the source follower transistor.
2. The readout circuit according to the claim 1 , wherein the pixel circuit is an active pixel sensor.
3. The readout circuit according to the claim 1 , wherein the negative voltage further meets a second equation: V_MINUS≥-V_GS.
4. The readout circuit according to the claim 1 , further comprising:
a correlated double sampling circuit, coupled to the output terminal of the biasing circuit.
5. The readout circuit according to the claim 4 , wherein the correlated double sampling circuit comprises:
a first switch circuit, wherein a first terminal of the first switch circuit is coupled to the output terminal of the biasing circuit;
a first capacitor, wherein a first terminal of the first capacitor is coupled to a second terminal of the first switch circuit, and a second terminal of the first capacitor is coupled to a ground voltage;
a second switch circuit, wherein a first terminal of the second switch circuit is coupled to the output terminal of the biasing circuit; and
a second capacitor, wherein a first terminal of the second capacitor is coupled to the second terminal of the second switch circuit, and a second terminal of the second capacitor is coupled to the ground voltage.
6. The readout circuit according to the claim 5 , wherein the negative voltage is equal to −0.6V.
7. The readout circuit according to the claim 4 , further comprising:
a switch capacitor amplifier circuit, coupled between the output terminal of the biasing circuit and the correlated double sampling circuit.
8. The readout circuit according to the claim 7 , wherein the switch capacitor amplifier circuit comprises:
a series capacitor, wherein a first terminal of the series capacitor is coupled to the output terminal of the biasing circuit;
an operational amplifier, wherein an inverting input terminal of the operational amplifier is coupled to the second terminal of the series capacitor, a non-inverting input terminal of the operational amplifier is coupled to a reference voltage, and an output terminal of operational amplifier is coupled to the correlated double sampling circuit;
a compensation capacitor, wherein a first terminal of the compensation capacitor is coupled to the inverting input terminal of the operational amplifier, and a second ten al of the compensation capacitor is coupled to the output terminal of the operational amplifier; and
a third switch circuit, wherein a first terminal of the third switch circuit is coupled to the inverting input terminal of the operational amplifier, and a second terminal of the third switch circuit is coupled to the output terminal of the operational amplifier.