Performance silicon carbide power devices
A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (μm). A width of the unit cell is one of less than and equal to 5.0 micrometers (μm). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.
1. A device comprising a unit cell on a silicon carbide (SiC) substrate, the unit cell comprising: a trench in a well region having a second conduction type, wherein a silicide layer is within the trench and in contact with a sidewall of the trench, wherein the well region is in contact with a region having a first conduction type to form a p-n junction; wherein the device comprises a first sinker region under the trench comprising the second conduction type, wherein the first sinker region comprises a first depth that is one of equal to and greater than a second depth of the well region; wherein a first width of the trench is less than 1.0 micrometers (μm); and wherein a second width of the unit cell is one of less than and equal to 5.0 micrometers (μm).
2. The device of claim 1 , wherein the device comprises a source region comprising the first conduction type.
3. The device of claim 2 , wherein the device comprises a metal oxide semiconductor field-effect transistor (MOSFET) component.
4. The device of claim 1 , wherein the device comprises a second sinker region comprising the second conduction type, the second sinker region comprises a third depth that is greater than the source region.
5. The device of claim 4 , wherein the third depth is greater than the second depth of the well region.
6. The device of claim 5 , wherein the third depth is less than the first depth of the first sinker region.
7. The device of claim 6 , wherein the trench comprises a fourth depth that is greater than the source region.
8. The device of claim 3 , further comprising: an interlevel dielectric (ILD) layer.
9. The device of claim 8 , wherein the SiC substrate is back grinded to a total thickness of one of 150 micrometers (μm) and 110 micrometers (μm).
10. The device of claim 8 , wherein the silicide layer is in contact with a horizontal surface of the source region.
11. The device of claim 8 , wherein the silicide layer is only in contact with a sidewall of the source region.
12. The device of claim 10 , wherein a lateral extent of an opening of the ILD layer is greater than the first width of the trench.
13. The device of claim 11 , wherein a lateral extent of an opening of the ILD layer equals the first width of the trench.
14. The device of claim 3 , wherein a MOSFET channel length is larger than 0.3 micrometers (μm), and a unit cell pitch comprises a lateral extent of one of less than and equal to 5.0 micrometers (μm).
15. The device of claim 1 , wherein a lateral spacing between adjacent well regions is less than 1.5 micrometers (μm), and a unit cell pitch comprises a lateral extent of one of less than and equal to 5.0 micrometers (μm).
16. The device of claim 12 , wherein the device comprises a first breakdown voltage less than 1700 Volts, wherein a first on-resistance measured at 175° C. on the device is less than 1.45 times a second on-resistance measured at 25° C.
17. The device of claim 12 , wherein the device comprises a second breakdown voltage less than 1000 Volts, wherein a third on-resistance measured at 175° C. on the device is less than 1.25 times a fourth on-resistance measured at 25° C.
18. The device of claim 12 , wherein the device comprises a fifth on-resistance of less than 4 milliohm centimeter squared, and a first short-circuit withstand time of greater than 2.5 microseconds (μs) at a first direct current (DC) link voltage of 800 Volts.
19. The device of claim 12 , wherein the device comprises a sixth on-resistance of less than 4 milliohm centimeter squared, and a second short-circuit withstand time of greater than 5.0 microseconds (μs) at a second direct current (DC) link voltage of 600 Volts.