Rectifier backflow reduction via biasing
Backflow in rectifiers may be reduced via biasing. Upon determining that backflow within a rectifier is likely, one or more rectifying elements in the rectifier may be debiased, via analog or digital means. The debiased rectifying elements become less conductive or nonconductive, thereby reducing or preventing backflow. The determination of backflow likelihood may be performed based on a signal to be backscattered or the amplitude-modulated envelope of an incident RF wave, and may be digital or analog in nature.
1. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:
an input node configured to receive an RF signal;
a rectifier for rectifying the RF signal and including a plurality of serially coupled rectifying elements defining a main current path; and
a processor block configured to:
determine RF signal amplitudes;
when a first amplitude of the RF signal indicates that rectifier backflow along the main current path is likely, couple a debiasing voltage to at least a first one of the rectifying elements to reduce a bias of the first rectifying element, thereby reducing a conductivity of the first rectifying element; and
subsequently, when a second amplitude of the RF signal indicates that backflow along the main current path is no longer likely, isolate the debiasing of the at least one rectifying element.
2. The RFID IC of claim 1 , further comprising at least one of:
an envelope detector; and
a current-starved common-gate, common-source amplifier, wherein the processor block is configured to determine the amplitude from one of the envelope detector and the amplifier.
3. The RFID IC of claim 1 , wherein the processor block is further configured to;
reduce the bias of the first rectifying element by causing a break in a resistive ladder structure configured to provide bias voltages to the at least one plurality of rectifying element elements in the rectifier; and
reduce the biases of the plurality of rectifying elements by causing the break.
4. The RFID IC of claim 1 , wherein:
the debiasing voltage is proportional to the first amplitude; and
the processor block is configured to reverse the debiasing of the first rectifying element by coupling a bias voltage proportional to the second amplitude to the first rectifying element.
5. The RFID IC of claim 1 , further comprising a bias-sampling capacitance coupled to the at least one rectifying element, wherein the processor block is further configured to:
use the bias-sampling capacitance to combine a first bias voltage of the first rectifying element with the debiasing voltage to reduce the bias of the first rectifying element.
6. The RFID IC of claim 1 , wherein:
the plurality of rectifying elements includes the first rectifying element and a second rectifying element associated with first and second bias-sampling capacitances, respectively;
the first and second rectifying elements have differing first and second bias voltages; and
the processor block is configured to:
use the first bias-sampling capacitor to combine the first bias voltage with the debiasing to reduce the bias of the first rectifying element; and
use the second bias-sampling capacitance to combine the second bias voltage with the debiasing voltage to reduce a bias of the second rectifying element.
7. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:
a rectifier including at least a first rectifying element, the rectifier configured to extract power from an incident RF signal;
an envelope detector configured to determine incident RF signal amplitudes; and
a processor block configured to:
receive a first RF signal amplitude from the envelope detector;
determine that the first RF signal amplitude is below a backflow threshold, and in response couple a debiasing voltage to at least the first rectifying element to reduce a bias of the first rectifying element, thereby reducing a conductivity of the first rectifying element and reducing backflow in the rectifier;
subsequently, receive a second RF signal amplitude from the envelope detector; and
determine that the second RF signal amplitude is above the backflow threshold, and in response isolate the debiasing voltage from the first rectifying element to increase the conductivity of the first rectifying element.
8. The RFID IC of claim 7 , further comprising a demodulator that includes the envelope detector.
9. The RFID IC of claim 7 , wherein the processor block is configured to reduce the bias of the first rectifying element by disconnecting a bias voltage from the first rectifying element.
10. The RFID IC of claim 9 , wherein the processor block is configured to:
disconnect the bias voltage by causing a break in a resistive ladder structure configured to provide bias voltages to a plurality of rectifying elements in the rectifier; and
reduce biases of the plurality of rectifying elements by causing the break.
11. The RFID IC of claim 7 , wherein:
the rectifier further includes a second rectifying element;
the first and second rectifying elements are associated with first and second bias-sampling capacitances, respectively;
the first and second rectifying elements have differing first and second bias voltages; and
the processor block is configured to:
use the first bias-sampling capacitance to combine the first bias voltage with the debiasing voltage to reduce a bias of the first rectifying element; and
use the second bias-sampling capacitance to combine the second bias voltage with the debiasing voltage to reduce a bias of the second rectifying element.
12. The RFID IC of claim 7 , wherein
the debiasing voltage is proportional to the first RF signal amplitude; and
the processor is further configured to increase the conductivity of the first rectifying element by coupling a bias voltage proportional to the second RF signal amplitude to the first rectifying element.
13. A method to reduce backflow in a Radio Frequency Identification (RFID) integrated circuit (IC) rectifier, the method comprising:
determining that a first value of an incident RF wave amplitude is below a threshold, and in response coupling a debiasing voltage to at least a first rectifying element in the rectifier to decrease a bias of the first rectifying element, thereby reducing a conductivity of the rectifying element and reducing backflow in the rectifier while the RF wave amplitude is below the threshold; and
subsequently, determining that a second value of the RF wave amplitude is above the threshold, and in response isolating the debiasing voltage from the at least first rectifying element to increase the conductivity of the first rectifying element.
14. The method of claim 13 , further comprising determining the RF wave amplitude using one of an envelope detector in the IC and a current-starved common-gate, common-source amplifier in the IC.
15. The method of claim 13 , wherein decreasing the bias of the first rectifying element further comprises disconnecting a bias voltage from the first rectifying element.
16. The method of claim 15 , wherein disconnecting the bias voltage comprises causing a break in a resistive ladder structure configured to provide bias voltages to a plurality of rectifying elements in the rectifier, the method further comprising decreasing biases of the plurality of rectifying elements by causing the break.
17. The method of claim 13 , further comprising:
sampling differing first and second bias voltages of first and second rectifying elements, respectively, in the rectifier;
reducing the bias of the first rectifying element using a combination formed from the sampled first bias voltage and the debiasing voltage;
reducing a bias of the second rectifying element using a combination formed from the sampled second bias voltage and the debiasing voltage.
18. The method of claim 13 , wherein:
the debiasing voltage is proportional to the first value; and
increasing the conductivity of the first rectifying element comprises coupling a bias voltage proportional to the second value to the first rectifying element.