Three-dimensional memory device with static random-access memory
Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In one example, the method for operating a 3D memory device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.
1. A method for operating a three-dimensional (3D) memory device comprising an input/output circuit, an array of on-die static random-access memory (SRAM) cells, functions as an on-die cache and an on-die data buffer, and an array of 3D NAND memory strings in a same chip, the method comprising:
transferring data through the input/output circuit to the array of on-die SRAM cells;
buffering the data in the array of on-die SRAM cells; and
programming the data into the array of 3D NAND memory strings from the array of on-die SRAM cells, wherein buffering the data in the array of on-die SRAM cells and programming the data into the array of 3D NAND memory strings are performed sequentially.
2. The method of claim 1 , further comprising transferring the data between the array of 3D NAND memory strings and the array of on-die SRAM cells through a plurality of bonding contacts.
3. The method of claim 1 , further comprising transferring the data from the array of on-die SRAM cells through the input/output circuit.
4. The method of claim 1 , wherein the data is transferred to the array of on-die SRAM cells sequentially, in groups, or in an arbitrary pattern.
5. The method of claim 1 , wherein, before programming the data into the array of 3D NAND memory strings, the method further comprises:
transmitting the data buffered in the array of on-die SRAM cells to a page buffer.
6. The method of claim 5 , wherein the page buffer is disposed in the same chip as the array of on-die SRAM cells and the array of 3D NAND memory strings.
7. The method of claim 1 , wherein the array of 3D NAND memory strings are configured as a plurality of planes, wherein each of the plurality of planes represents a set of memory cells formed by a word line and a set of intersecting memory strings.
8. The method of claim 7 , wherein a plane comprises a plurality of pages of memory cells.
9. The method of claim 8 , wherein the data is programmed into the array of 3D NAND memory strings in pages.
10. The method of claim 9 , wherein the array of on-die SRAM cells are configured as a plurality of buffer units, wherein each of the plurality of buffer units is configured to buffer data for programming a page in the array of 3D NAND memory strings.
11. A method for operating a three-dimensional (3D) memory device comprising an input/output circuit, an array of on-die static random-access memory (SRAM) cells, functions as an on-die cache and an on-die data buffer, and an array of 3D NAND memory strings in a same chip, the method comprising:
transferring data through the input/output circuit to the array of on-die SRAM cells;
buffering the data in the array of on-die SRAM cells; and
programming the data into the array of 3D NAND memory strings from the array of on-die SRAM cells, wherein buffering the data in the array of on-die SRAM cells and programming the data into the array of 3D NAND memory strings are performed at a same time.
12. The method of claim 11 , further comprising transferring the data between the array of 3D NAND memory strings and the array of on-die SRAM cells through a plurality of bonding contacts.
13. The method of claim 11 , further comprising transferring the data from the array of on-die SRAM cells through the input/output circuit.
14. The method of claim 11 , wherein the data is transferred to the array of on-die SRAM cells sequentially, in groups, or in an arbitrary pattern.
15. The method of claim 11 , wherein, before programming the data into the array of 3D NAND memory strings, the method further comprises:
transmitting the data buffered in the array of on-die SRAM cells to a page buffer.
16. The method of claim 15 , wherein the page buffer is disposed in the same chip as the array of on-die SRAM cells and the array of 3D NAND memory strings.
17. The method of claim 11 , wherein the array of 3D NAND memory strings are configured as a plurality of planes, wherein each of the plurality of planes represents a set of memory cells formed by a word line and a set of intersecting memory strings.
18. The method of claim 17 , wherein a plane comprises a plurality of pages of memory cells.
19. The method of claim 18 , wherein the data is programmed into the array of 3D NAND memory strings in pages.
20. The method of claim 19 , wherein the array of on-die SRAM cells are configured as a plurality of buffer units, wherein each of the plurality of buffer units is configured to buffer data for programming a page in the array of 3D NAND memory strings.