Signal receiving circuit, memory storage device and calibration method of equalizer circuit

1. A signal receiving circuit comprising:

an equalizer circuit configured to receive a first signal and adjust the first signal according to a control parameter to output a second signal;

a clock and data recovery circuit coupled to the equalizer circuit and configured to generate a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and

a calibration control circuit coupled to the equalizer circuit and the clock and data recovery circuit,

wherein the calibration control circuit is configured to generate a second sampling signal according to a second reference signal and the second signal and adjust the control parameter according to the second sampling signal to calibrate the equalizer circuit, and

wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal,

wherein the operation of adjusting the control parameter by the calibration control circuit comprises:

adjusting a low frequency gain of the equalizer circuit or a high frequency gain of the equalizer circuit.

2. The signal receiving circuit according to claim 1 , wherein the calibration control circuit comprises:

a comparison circuit configured to compare the second reference signal and the second signal to generate the second sampling signal; and

a decision circuit coupled to the comparison circuit and configured to determine a count value according to the second sampling signal, wherein the count value reflects a total number of a first sampled value in the second sampling signal, and

the decision circuit is further configured to adjust the control parameter according to the count value.

3. The signal receiving circuit according to claim 2 , wherein the operation of adjusting the control parameter according to the count value by the decision circuit comprises:

after N sampled values in the second sampling signal are analyzed, if the count value does not meet a default condition, resetting the count value and adjusting the control parameter; and

after the N sampled values in the second sampling signal are analyzed, if the count value meets the default condition, recording the control parameter.

4. The signal receiving circuit according to claim 1 , wherein the operation of adjusting the low frequency gain of the equalizer circuit or the high frequency gain of the equalizer circuit by the calibration control circuit comprises:

determining whether the first signal is a low frequency signal or a high frequency signal according to the first sampling signal;

if the first signal is the low frequency signal, adjusting the low frequency gain of the equalizer circuit; and

if the first signal is the high frequency signal, adjusting the high frequency gain of the equalizer circuit.

5. The signal receiving circuit according to claim 1 , wherein the operation of adjusting the low frequency gain of the equalizer circuit or the high frequency gain of the equalizer circuit by the calibration control circuit comprises:

obtaining a low frequency signal according to the first sampling signal;

adjusting the low frequency gain of the equalizer circuit according to the low frequency signal;

obtaining a high frequency signal according to the first sampling signal; and

adjusting the high frequency gain of the equalizer circuit according to the high frequency signal.

6. The signal receiving circuit according to claim 1 , further comprising:

a reference signal adjustment circuit coupled to the calibration control circuit and configured to adjust the voltage value of the second reference signal.

7. The signal receiving circuit according to claim 1 , wherein the voltage value of the second reference signal is farther away from an oscillation center voltage of the second signal than the voltage value of the first reference signal.

8. A memory storage device comprising:

a connection interface unit configured to couple a host system;

a rewritable non-volatile memory module;

a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module; and

a signal receiving circuit disposed in the connection interface unit,

wherein the signal receiving circuit comprises an equalizer circuit and the signal receiving circuit is configured to receive a first signal,

the equalizer circuit is configured to adjust the first signal according to a control parameter to output a second signal,

the signal receiving circuit is further configured to generate a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal,

the signal receiving circuit is further configured to generate a second sampling signal according to a second reference signal and the second signal and adjust the control parameter according to the second sampling signal to calibrate the equalizer circuit, and

wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal,

wherein the operation of adjusting the control parameter by the signal receiving circuit comprises:

adjusting a low frequency gain of the equalizer circuit or a high frequency gain of the equalizer circuit.

9. The memory storage device according to claim 8 , wherein the signal receiving circuit further comprises:

a comparison circuit configured to compare the second reference signal and the second signal to generate the second sampling signal; and

a decision circuit coupled to the comparison circuit and configured to determine a count value according to the second sampling signal, wherein the count value reflects a total number of a first sampled value in the second sampling signal, and

the decision circuit is further configured to adjust the control parameter according to the count value.

10. The memory storage device according to claim 9 , wherein the operation of adjusting the control parameter according to the count value by the decision circuit comprises:

after N sampled values in the second sampling signal are analyzed, if the count value does not meet a default condition, resetting the count value and adjusting the control parameter; and

after the N sampled values in the second sampling signal are analyzed, if the count value meets the default condition, recording the control parameter.

11. The memory storage device according to claim 8 , wherein the operation of adjusting the low frequency gain of the equalizer circuit or the high frequency gain of the equalizer circuit by the signal receiving circuit comprises:

determining whether the first signal is a low frequency signal or a high frequency signal according to the first sampling signal;

if the first signal is the low frequency signal, adjusting the low frequency gain of the equalizer circuit; and

if the first signal is the high frequency signal, adjusting the high frequency gain of the equalizer circuit.

12. The memory storage device according to claim 8 , wherein the operation of adjusting the low frequency gain of the equalizer circuit or the high frequency gain of the equalizer circuit by the signal receiving circuit comprises:

obtaining a low frequency signal according to the first sampling signal;

adjusting the low frequency gain of the equalizer circuit according to the low frequency signal;

obtaining a high frequency signal according to the first sampling signal; and

adjusting the high frequency gain of the equalizer circuit according to the high frequency signal.

13. The memory storage device according to claim 8 , wherein the signal receiving circuit is further configured to adjust the voltage value of the second reference signal.

14. The memory storage device according to claim 8 , wherein the voltage value of the second reference signal is farther away from an oscillation center voltage of the second signal than the voltage value of the first reference signal.

15. A calibration method of an equalizer circuit for a memory storage device, wherein the calibration method comprises:

receiving a first signal;

adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal;

generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and

generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit,

wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal,

wherein the step of adjusting the control parameter comprises:

adjusting a low frequency gain of the equalizer circuit or a high frequency gain of the equalizer circuit.

16. The calibration method according to claim 15 , wherein the step of generating the second sampling signal according to the second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit comprises:

comparing the second reference signal and the second signal to generate the second sampling signal;

determining a count value according to the second sampling signal, wherein the count value reflects a total number of a first sampled value in the second sampling signal; and

adjusting the control parameter according to the count value.

17. The calibration method according to claim 16 , wherein the step of adjusting the control parameter according to the count value comprises:

after N sampled values in the second sampling signal are analyzed, if the count value does not meet a default condition, resetting the count value and adjusting the control parameter; and

after the N sampled values in the second sampling signal are analyzed, if the count value meets the default condition, recording the control parameter.

18. The calibration method according to claim 13 , wherein the step of adjusting the low frequency gain of the equalizer circuit or the high frequency gain of the equalizer circuit comprises:

determining whether the first signal is a low frequency signal or a high frequency signal according to the first sampling signal;

if the first signal is the low frequency signal, adjusting the low frequency gain of the equalizer circuit; and

if the first signal is the high frequency signal, adjusting the high frequency gain of the equalizer circuit.

19. The calibration method according to claim 15 , wherein the step of adjusting the low frequency gain of the equalizer circuit or the high frequency gain of the equalizer circuit comprises:

obtaining a low frequency signal according to the first sampling signal;

adjusting the low frequency gain of the equalizer circuit according to the low frequency signal;

obtaining a high frequency signal according to the first sampling signal; and

adjusting the high frequency gain of the equalizer circuit according to the high frequency signal.

20. The calibration method according to claim 15 , further comprising:

adjusting the voltage value of the second reference signal by a reference signal adjustment circuit.

21. The calibration method according to claim 15 , wherein the voltage value of the second reference signal is farther away from an oscillation center voltage of the second signal than the voltage value of the first reference signal.