Variable latency instructions
Techniques related to executing instructions by a processor comprising receiving a first instruction for execution, determining a first latency value based on an expected amount of time needed for the first instruction to be executed, storing the first latency value in a writeback queue, beginning execution of the first instruction on the instruction execution pipeline, adjusting the latency value based on an amount of time passed since beginning execution of the first instruction, outputting a first result of the first instruction based on the latency value, receiving a second instruction, determining that the second instruction is a variable latency instruction, storing a ready value indicating that a second result of the second instruction is not ready in the writeback queue, beginning execution of the second instruction on the instruction execution pipeline, updating the ready value to indicate that the second result is ready, and outputting the second result.
1. A method for executing a plurality of instructions by a processor, the method comprising:
receiving a first instruction for execution on an instruction execution pipeline;
determining whether to store a first latency value or a first ready value of the first instruction in a writeback queue based on whether the first instruction is non-variable latency or variable latency;
based on the first instruction being non-variable latency:
prior to the execution of the first instruction, determining the first latency value based on an expected amount of time needed for the execution of the first instruction;
storing the first latency value in the writeback queue;
beginning the execution of the first instruction on the instruction execution pipeline;
adjusting the first latency value based on an amount of time passed since the beginning of the execution of the first instruction; and
outputting a first result of the first instruction based on the first latency value;
receiving a second instruction for execution on the instruction execution pipeline;
determining whether to store a second latency value or a second ready value of the second instruction in the writeback queue based on whether the second instruction is non-variable latency or variable latency; and
based on the second instruction being variable latency:
storing the second ready value indicating that a second result of the second instruction is not ready in the writeback queue;
beginning the execution of the second instruction on the instruction execution pipeline;
updating the second ready value to indicate that the second result is ready based on a determination that the execution of the second instruction has completed; and
outputting the second result.
2. The method of claim 1 , wherein the second instruction comprises a memory operation.
3. The method of claim 2 , wherein the memory operation comprises loading data from a memory, and the method further comprising:
receiving one or more portions of the data from the memory;
assembling the one or more portions of the data in the writeback queue as the one or more portions are received; and
outputting the data after assembling the data from the one or more portions of the data.
4. The method of claim 1 , wherein the second instruction comprises a divide or modulus instruction.
5. The method of claim 4 , wherein the second ready value is stored in a dedicated writeback queue.
6. The method of claim 1 , wherein the expected amount of time is based on a number of processor cycles in which the respective instruction can be completed in.
7. The method of claim 1 , further comprising:
receiving a third instruction for execution on the instruction execution pipeline before the execution of the second instruction has completed; and
stalling the execution of the third instruction until the execution of the second instruction has completed.
8. The method of claim 7 , wherein stalling the execution of the third instruction is based on the second ready value.
9. A processor, comprising:
an instruction execution pipeline having a plurality of pipeline stages; and
pipeline circuitry configured to:
receive a first instruction for execution on the instruction execution pipeline;
determine whether to store a first latency value or a first ready value of the first instruction in a writeback queue based on whether the first instruction is non-variable latency or variable latency;
based on the first instruction being non-variable latency:
determine the first latency value based on an expected amount of time needed for the execution of the first instruction;
store the first latency value in the writeback queue;
begin the execution of the first instruction on the instruction execution pipeline;
adjust the first latency value based on an amount of time passed since the beginning of the execution of the first instruction; and
output a first result of the first instruction based on the first latency value;
receive a second instruction for execution on the instruction execution pipeline;
determine whether to store a second latency value or a second ready value of the second instruction in the writeback queue based on whether the second instruction is non-variable latency or variable latency; and
based on the second instruction being variable latency:
store the second ready value indicating that a second result of the second instruction is not ready in the writeback queue;
begin the execution of the second instruction on the instruction execution pipeline;
update the second ready value to indicate that the second result is ready based on a determination that the execution of the second instruction has completed; and
output the second result.
10. The processor of claim 9 , wherein the second instruction comprises a memory operation.
11. The processor of claim 10 , wherein the memory operation comprises loading data from a memory, and wherein the pipeline circuitry is further configured to:
receive one or more portions of the data from the memory;
assemble the one or more portions of the data in the writeback queue as the one or more portions are received; and
output the data after assembling the data from the one or more portions of the data.
12. The processor of claim 9 , wherein the second instruction comprises a divide or modulus instruction.
13. The processor of claim 12 , wherein the second ready value is stored in a dedicated writeback queue.
14. The processor of claim 9 , wherein the expected amount of time is based on a number of processor cycles in which the respective instruction can be completed in.
15. The processor of claim 9 , wherein the pipeline circuitry is further configured to:
receive a third instruction for execution on the instruction execution pipeline before execution of the second instruction has completed; and
stall the execution of the third instruction until the execution of the second instruction has completed.
16. A processing system comprising:
a memory; and
a processor comprising:
an instruction execution pipeline having a plurality of pipeline stages; and
pipeline circuitry configured to:
receive a first instruction for execution on the instruction execution pipeline;
determine whether to store a first latency value or a first ready value of the first instruction in a writeback queue based on whether the first instruction is non-variable latency or variable latency;
based on the first instruction being non-variable latency:
determine the first latency value based on an expected amount of time needed for the execution of the first instruction;
store the first latency value in the writeback queue;
begin the execution of the first instruction on the instruction execution pipeline;
adjust the first latency value based on an amount of time passed since the beginning of the execution of the first instruction; and
output a first result of the first instruction based on the first latency value;
receive a second instruction for execution on the instruction execution pipeline;
determine whether to store a second latency value or a second ready value of the second instruction in the writeback queue based on whether the second instruction is non-variable latency or variable latency; and
based on the second instruction being variable latency:
store the second ready value indicating that a second result of the second instruction is not ready in the writeback queue;
begin the execution of the second instruction on the instruction execution pipeline;
update the second ready value to indicate that the second result is ready based on a determination that the execution of the second instruction has completed; and
output the second result.
17. The processing system of claim 16 , wherein the second instruction comprises a memory operation.
18. The processing system of claim 17 , wherein the memory operation comprises loading data from the memory, and wherein the pipeline circuitry is further configured to:
receive one or more portions of the data from the memory;
assemble the one or more portions of the data in the writeback queue as the one or more portions are received; and
output the data after assembling the data from the one or more portions of the data.
19. The processing system of claim 16 , wherein the second instruction comprises a divide or modulus instruction.
20. The processing system of claim 19 , wherein the second ready value is stored in a dedicated writeback queue.