Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology
A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
1. A method comprising:
writing a private key of a public-private key pair with a corresponding identity to an integrated circuit comprising a processor, a non-volatile memory, and a cryptographic engine coupled to said processor and said non-volatile memory, said private key being written to said non-volatile memory, said integrated circuit being implemented in complementary metal-oxide semiconductor 14 nm or smaller technology;
modifying said non-volatile memory to be one-time programmable by inducing a threshold voltage shift in transistors of said non-volatile memory, subsequent to said writing, and to inhibit at least one of reverse engineering and tampering; and
permanently modifying said integrated circuit, subsequent to said writing, such that further writing to said non-volatile memory is disabled and such that said private key can be read only by said cryptographic engine and not off-chip.
2. The method of claim 1 , wherein, in said writing step, said non-volatile memory is dedicated to said private key.
3. The method of claim 1 , further comprising inducing oxide breakdown in transistors of said non-volatile memory, subsequent to said writing, to inhibit at least one of the reverse engineering and the tampering.
4. The method of claim 1 , further comprising, subsequent to said permanent modification:
providing said private key from said non-volatile memory to said cryptographic engine; and
using said private key from said non-volatile memory to respond to a challenge question.
5. The method of claim 1 , further comprising, subsequent to said permanent modification:
providing said private key from said non-volatile memory to said cryptographic engine; and
using said private key from said non-volatile memory to carry out decryption.
6. The method of claim 1 , further comprising, subsequent to said permanent modification:
providing said private key from said non-volatile memory to said cryptographic engine; and
using said private key from said non-volatile memory to carry out encryption.
7. The method of claim 1 , wherein said writing is carried out with a write circuit of said non-volatile memory, and wherein said permanently modifying said integrated circuit such that further writing to said non-volatile memory is disabled comprises disabling said write circuit with an electrical fuse.
8. The method of claim 1 , wherein said writing is carried out with a dedicated pin of said non-volatile memory, and wherein said permanently modifying said integrated circuit such that further writing to said non-volatile memory is disabled comprises removing said dedicated pin.
9. An integrated circuit comprising:
a processor;
a non-volatile memory storing a private key of a public-private key pair; and
a cryptographic engine coupled to said processor and said non-volatile memory;
wherein:
said integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology;
said integrated circuit is permanently configured such that further writing to said non-volatile memory, beyond said private key, is disabled;
said integrated circuit is permanently configured to induce oxide breakdown in transistors of said non-volatile memory, subsequent to said writing, to inhibit at least one of reverse engineering and tampering; and
said integrated circuit is permanently configured such that said private key can be read only by said cryptographic engine and not off-chip.
10. The integrated circuit of claim 9 , wherein said non-volatile memory is dedicated to said private key.
11. The integrated circuit of claim 9 , wherein said non-volatile memory comprises metal oxide semiconductor field effect transistors having dielectrics, and wherein said dielectrics have charges trapped therein to provide a threshold voltage shift in said transistors, to inhibit the reverse engineering.
12. The integrated circuit of claim 9 , wherein said non-volatile memory comprises metal oxide semiconductor field effect transistors exhibiting oxide breakdown to inhibit the reverse engineering.
13. The integrated circuit of claim 9 , further comprising a write circuit of said non-volatile memory, isolated by a blown electrical fuse.
14. An integrated circuit comprising:
a processor;
a non-volatile memory storing a private key of a public-private key pair;
a cryptographic engine coupled to said processor and said non-volatile memory; and
an unblown electrical fuse structure;
wherein:
said integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology;
said integrated circuit is configured such that further writing to said non-volatile memory, beyond said private key, is disabled when said fuse structure is blown; and
said integrated circuit is configured such that subsequent to blowing of said fuse structure, said private key can be read only by said cryptographic engine and not off-chip, said private key in said non-volatile memory being encoded using two-bit encoding to inhibit at least one of reverse engineering and tampering.
15. The integrated circuit of claim 14 , wherein said non-volatile memory is dedicated to said private key.