IP Library › Granted Patent US 11,218,167

Granted Patent B2

US 11,218,167 · App. 16/757,824 · Granted Jan 4, 2022

Transmission device, transmission method, reception device, and reception method

Inventors: Makiko Yamamoto (Tokyo, JP); Yuji Shinohara (Kanagawa, JP)

Assignee: SONY CORPORATION

H03M13/1148 H03M13/1105 H03M13/616 H04L1/0063

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Quick Facts

Patent No.: US 11,218,167
App. No.: 16/757,824
Granted: Jan 4, 2022
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 9/16 or 10/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns. The present technology can be applied to data transmission using an LDPC code.

Claims (332)

1. A transmission device comprising:

encoding circuitry configured to perform LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 9/16, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

291 817 1023 1118 1168 1195 1419 1763 2507 3005

3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301

6600 6644 7052 7093 7105 7487

133 565 957 1018 1150 1196 1210 1224 1361 1484 2330

2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399

5421 5545 6972 7156

129 365 541 1026 1199 1527 2467 3386 3458 4215 4438

4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745

6973 7251 7329 7336

996 1392 2493 2910 3048 3281 4969 5189 5632 6236

6983

165 2521 2650 2824 3493 4637 5670 6470

266 345 390 2365 2843 3274 4321 5165

245 2173 2274 2687 3763 4284 5562 6564

2787 2970 3503

691 3718 5047

593 969 3593

331 3809 6269

1627 2886 5935

1046 2976 4457

4725 6028 6458

6172 6610 7530

1536 7102 7148

233 2463 4955

826 4319 6969

3073 6675 6774

407 4251 7087

1380 3802 4937

1911 4360 6306

4027 6219 7292

398 1190 1936

250 830 7241

5500 5828 7478

1261 4649 7237.

2. A transmission method comprising:

performing, by encoding circuitry, LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 9/16, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

291 817 1023 1118 1168 1195 1419 1763 2507 3005

3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301

6600 6644 7052 7093 7105 7487

133 565 957 1018 1150 1196 1210 1224 1361 1484 2330

2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399

5421 5545 6972 7156

129 365 541 1026 1199 1527 2467 3386 3458 4215 4438

4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745

6973 7251 7329 7336

996 1392 2493 2910 3048 3281 4969 5189 5632 6236

6983

165 2521 2650 2824 3493 4637 5670 6470

266 345 390 2365 2843 3274 4321 5165

245 2173 2274 2687 3763 4284 5562 6564

2787 2970 3503

691 3718 5047

593 969 3593

331 3809 6269

1627 2886 5935

1046 2976 4457

4725 6028 6458

6172 6610 7530

1536 7102 7148

233 2463 4955

826 4319 6969

3073 6675 6774

407 4251 7087

1380 3802 4937

1911 4360 6306

4027 6219 7292

398 1190 1936

250 830 7241

5500 5828 7478

1261 4649 7237.

3. A reception device comprising:

decoding circuitry configured to decode an LDPC code with a code length N of 17280 bits and a coding rate r of 9/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

291 817 1023 1118 1168 1195 1419 1763 2507 3005

3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301

6600 6644 7052 7093 7105 7487

133 565 957 1018 1150 1196 1210 1224 1361 1484 2330

2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399

5421 5545 6972 7156

129 365 541 1026 1199 1527 2467 3386 3458 4215 4438

4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745

6973 7251 7329 7336

996 1392 2493 2910 3048 3281 4969 5189 5632 6236

6983

165 2521 2650 2824 3493 4637 5670 6470

266 345 390 2365 2843 3274 4321 5165

245 2173 2274 2687 3763 4284 5562 6564

2787 2970 3503

691 3718 5047

593 969 3593

331 3809 6269

1627 2886 5935

1046 2976 4457

4725 6028 6458

6172 6610 7530

1536 7102 7148

233 2463 4955

826 4319 6969

3073 6675 6774

407 4251 7087

1380 3802 4937

1911 4360 6306

4027 6219 7292

398 1190 1936

250 830 7241

5500 5828 7478

1261 4649 7237.

4. A reception method comprising:

decoding, by decoding circuitry, an LDPC code with a code length N of 17280 bits and a coding rate r of 9/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

291 817 1023 1118 1168 1195 1419 1763 2507 3005

3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301

6600 6644 7052 7093 7105 7487

133 565 957 1018 1150 1196 1210 1224 1361 1484 2330

2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399

5421 5545 6972 7156

129 365 541 1026 1199 1527 2467 3386 3458 4215 4438

4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745

6973 7251 7329 7336

996 1392 2493 2910 3048 3281 4969 5189 5632 6236

6983

165 2521 2650 2824 3493 4637 5670 6470

266 345 390 2365 2843 3274 4321 5165

245 2173 2274 2687 3763 4284 5562 6564

2787 2970 3503

691 3718 5047

593 969 3593

331 3809 6269

1627 2886 5935

1046 2976 4457

4725 6028 6458

6172 6610 7530

1536 7102 7148

233 2463 4955

826 4319 6969

3073 6675 6774

407 4251 7087

1380 3802 4937

1911 4360 6306

4027 6219 7292

398 1190 1936

250 830 7241

5500 5828 7478

1261 4649 7237.

5. A transmission device comprising:

encoding circuitry configured to perform LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 10/16, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

579 608 613 760 795 839 910 1895 2239 2535 2670

2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166

6352

263 291 694 1172 1232 1925 2657 3037 3057 3400 3550

3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157

6227

527 601 1254 1476 1760 2070 2099 2725 2961 3529

3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087

6446

235 319 480 2036 2188 2358 2423 2510 2911 3225 3472

3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477

1809 2974 3464 5295 5490 5671

2148 3629 4304 4854 4876 6037

2031 2246 3358 4679 6125 6331

874 2483 2964 3872 4509 4904

4001 4303 5079

1652 4524 5263

2551 3381 5524

713 1908 6304

2722 3347 6201

433 923 5564

2181 4242 6202

51 2711 4435

414 708 5539

2222 5036 5974

784 3588 5125

4256 5004 5540

1761 2781 6037

1547 2266 4377

4109 5836 6337

767 2468 4764

2528 5457 5872

884 4651 4807

161 3582 5164

744 2624 4852

239 1740 5807

33 3595 5121.

6. A transmission method comprising:

performing, by encoding circuitry, LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 10/16, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

579 608 613 760 795 839 910 1895 2239 2535 2670

2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166

6352

263 291 694 1172 1232 1925 2657 3037 3057 3400 3550

3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157

6227

527 601 1254 1476 1760 2070 2099 2725 2961 3529

3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087

6446

235 319 480 2036 2188 2358 2423 2510 2911 3225 3472

3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477

1809 2974 3464 5295 5490 5671

2148 3629 4304 4854 4876 6037

2031 2246 3358 4679 6125 6331

874 2483 2964 3872 4509 4904

4001 4303 5079

1652 4524 5263

2551 3381 5524

713 1908 6304

2722 3347 6201

433 923 5564

2181 4242 6202

51 2711 4435

414 708 5539

2222 5036 5974

784 3588 5125

4256 5004 5540

1761 2781 6037

1547 2266 4377

4109 5836 6337

767 2468 4764

2528 5457 5872

884 4651 4807

161 3582 5164

744 2624 4852

239 1740 5807

33 3595 5121.

7. A reception device comprising:

decoding circuitry configured to decode an LDPC code with a code length N of 17280 bits and a coding rate r of 10/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

579 608 613 760 795 839 910 1895 2239 2535 2670

2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166

6352

263 291 694 1172 1232 1925 2657 3037 3057 3400 3550

3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157

6227

527 601 1254 1476 1760 2070 2099 2725 2961 3529

3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087

6446

235 319 480 2036 2188 2358 2423 2510 2911 3225 3472

3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477

1809 2974 3464 5295 5490 5671

2148 3629 4304 4854 4876 6037

2031 2246 3358 4679 6125 6331

874 2483 2964 3872 4509 4904

4001 4303 5079

1652 4524 5263

2551 3381 5524

713 1908 6304

2722 3347 6201

433 923 5564

2181 4242 6202

51 2711 4435

414 708 5539

2222 5036 5974

784 3588 5125

4256 5004 5540

1761 2781 6037

1547 2266 4377

4109 5836 6337

767 2468 4764

2528 5457 5872

884 4651 4807

161 3582 5164

744 2624 4852

239 1740 5807

33 3595 5121.

8. A reception method comprising:

decoding, by decoding circuitry, an LDPC code with a code length N of 17280 bits and a coding rate r of 10/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein

the LDPC code includes information bits and parity bits,

the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,

the information matrix portion is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

579 608 613 760 795 839 910 1895 2239 2535 2670

2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166

6352

263 291 694 1172 1232 1925 2657 3037 3057 3400 3550

3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157

6227

527 601 1254 1476 1760 2070 2099 2725 2961 3529

3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087

6446

235 319 480 2036 2188 2358 2423 2510 2911 3225 3472

3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477

1809 2974 3464 5295 5490 5671

2148 3629 4304 4854 4876 6037

2031 2246 3358 4679 6125 6331

874 2483 2964 3872 4509 4904

4001 4303 5079

1652 4524 5263

2551 3381 5524

713 1908 6304

2722 3347 6201

433 923 5564

2181 4242 6202

51 2711 4435

414 708 5539

2222 5036 5974

784 3588 5125

4256 5004 5540

1761 2781 6037

1547 2266 4377

4109 5836 6337

767 2468 4764

2528 5457 5872

884 4651 4807

161 3582 5164

744 2624 4852

239 1740 5807

33 3595 5121.

Assignments (2)

CHANGE OF NAME Recorded Dec 6, 2022

From: SONY CORPORATION

To: SONY GROUP CORPORATION

Reel/Frame 062416/0692 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2020

From: YAMAMOTO, MAKIKO; SHINOHARA, YUJI

To: SONY CORPORATION

Reel/Frame 053828/0825 →

Priority Claims (1)

JP JP2017-209876 · Oct 31, 2017 · national

Continuity (1)

Related Publication 20210194502A1 · Jun 24, 2021