IP Library Granted Patent US 11,218,320
Granted Patent B2
US 11,218,320 · App. 16/455,908 · Granted Jan 4, 2022

Accelerators for post-quantum cryptography secure hash-based signing and verification

Inventors: Vikram Suresh (Portland, OR); Sanu Mathew (Portland, OR); Manoj Sastry (Portland, OR); Santosh Ghosh (Hillsboro, OR); Raghavan Kumar (Hillsboro, OR); Rafael Misoczki (Hillsboro, OR)
Assignee: INTEL CORPORATION
H04L9/3239H04L9/0869H04L9/3247H04L2209/38
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Quick Facts
Patent No.
US 11,218,320
App. No.
16/455,908
Granted
Jan 4, 2022
Kind
B2
Abstract

In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

Claims (75)

1. An apparatus, comprising:

a computer readable memory;

hash logic to:

generate a message hash value based on an input message;

compute the message hash of the input message using a secure hash algorithm (SHA2) hash function; and

process the message hash to generate an array of values;

signature logic to:

generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key; and

apply a chain function to the private key, the chain function comprising a chain of SHA2 hash operations, wherein hash operations in the chain of SHA2 hash operations comprises:

a first pseudo-random function (PRF) to generate a bitmask and a second PRF to generate a key;

an XOR logic to XOR the bitmask with a hash value from a previous hash function to generate an XOR output; and

a SHA2 hash function to receive a concatenation of the XOR output and the bitmask as an input and to generate a hash output; and

accelerator logic to pre-compute at least one set of inputs to the signature logic.

2. The apparatus of claim 1 , the accelerator logic to:

precompute a first intermediate hash value based on an OPCODE input and a SEED input; and

apply the first intermediate hash value to the first PRF and the second PRF in the chain of SHA2 hash operations in the signature logic.

3. The apparatus of claim 2 , the accelerator logic to:

precompute a second intermediate hash value based on a portion of an address input; and

apply the second intermediate hash value to the first PRF and the second PRF in the chain of SHA2 hash operations in the signature logic.

4. The apparatus of claim 3 , the accelerator logic to:

precompute a third intermediate hash value based on a portion of an address input; and

apply the third intermediate hash value to the first SHA2 hash function in the chain of SHA2 hash operations in the signature logic.

5. The apparatus of claim 1 , the signature logic to:

apply a L-tree operation which generates a binary tree to compress the public key into a single leaf node value using a series of keyed hash operations, wherein hash operations in the series of keyed hash operations comprises:

a first pseudo-random function (PRF) to generate a first bitmask;

a second PRF to generate a second bitmask;

a third PRF to generate a key;

a first XOR logic to XOR the first bitmask with a first public key value from to generate a first XOR output;

a second XOR logic to XOR the second bitmask with a second public key value from to generate a second XOR output and

a SHA2 hash function to receive a concatenation of the first XOR output, the second XOR output, an OPCODE and PAD as an input and to generate a hash output.

6. The apparatus of claim 5 , the accelerator logic to:

precompute a first intermediate hash value based on an OPCODE input and a SEED input; and

apply the first intermediate hash value to the first PRF, the second PRF, and the third PRF in the series of SHA2 hash operations in the L-Tree operation.

7. The apparatus of claim 6 , the accelerator logic to:

precompute a second intermediate hash value based on a portion of an address input; and

apply the second intermediate hash value to the first PRF, the second PRF, and the third PRF in the series of SHA2 hash operations in the L-Tree operation.

8. The apparatus of claim 7 , the accelerator logic to:

precompute a third intermediate hash value based on a portion of an address input; and

apply the third intermediate hash value to the SHA2 hash function in the series of SHA2 hash operations in the L-Tree operation.

9. A computer-implemented method, comprising:

generating a message hash value based on an input message;

computing the message hash of the input message using a secure hash algorithm (SHA2) hash function;

processing the message hash to generate an array of values;

generating a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key;

applying a chain function to the private key, the chain function comprising a chain of SHA2 hash operations, wherein hash operations in the chain of SHA2 hash operations comprises:

a first pseudo-random function (PRF) to generate a bitmask and a second PRF to generate a key;

an XOR logic to XOR the bitmask with a hash value from a previous hash function to generate an XOR output; and

a SHA2 hash function to receive a concatenation of the XOR output and the bitmask as an input and to generate a hash output; and

pre-computing at least one set of inputs to the signature logic.

10. The method of claim 9 , further comprising:

precomputing a first intermediate hash value based on an OPCODE input and a SEED input; and

applying the first intermediate hash value to the first PRF and the second PRF in the chain of SHA2 hash operations in the signature logic.

11. The method of claim 10 , further comprising:

precomputing a second intermediate hash value based on a portion of an address input; and

applying the second intermediate hash value to the first PRF and the second PRF in the chain of SHA2 hash operations in the signature logic.

12. The method of claim 11 , further comprising:

precomputing a third intermediate hash value based on a portion of an address input; and

applying the third intermediate hash value to the first SHA2 hash function in the chain of SHA2 hash operations in the signature logic.

13. The method of claim 9 , further comprising:

apply a L-tree operation which generates a binary tree to compress the public key into a single leaf node value using a series of keyed hash operations, wherein hash operations in the series of keyed hash operations comprises:

a first pseudo-random function (PRF) to generate a first bitmask;

a second PRF to generate a second bitmask;

a third PRF to generate a key;

a first XOR logic to XOR the first bitmask with a first public key value from to generate a first XOR output;

a second XOR logic to XOR the second bitmask with a second public key value from to generate a second XOR output; and

a SHA2 hash function to receive a concatenation of the first XOR output, the second XOR output, an OPCODE and PAD as an input and to generate a hash output.

14. The method of claim 13 , further comprising:

precomputing a first intermediate hash value based on an OPCODE input and a SEED input; and

applying the first intermediate hash value to the first PRF, the second PRF, and the third PRF in the series of SHA2 hash operations in the L-Tree operation.

15. The method of claim 14 , further comprising:

precomputing a second intermediate hash value based on a portion of an address input; and

applying the second intermediate hash value to the first PRF, the second PRF, and the third PRF in the series of SHA2 hash operations in the L-Tree operation.

16. The method of claim 15 , further comprising:

precomputing a third intermediate hash value based on a portion of an address input; and

applying the third intermediate hash value to the SHA2 hash function in the series of SHA2 hash operations in the L-Tree operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2019
From: SURESH, VIKRAM; MATHEW, SANU; SASTRY, MANOJ; GHOSH, SANTOSH; KUMAR, RAGHAVAN; MISOCZKI, RAFAEL
To: INTEL CORPORATION
Reel/Frame 051084/0165 →
Continuity (1)
Related Publication 20190319797A1 · Oct 17, 2019