High voltage isolation structure and method
Described examples include a microelectronic device with a high voltage capacitor that includes a high voltage node, a low voltage node, a first dielectric disposed between the low voltage node and the high voltage node, a first conductive plate disposed between the first dielectric and the high voltage node, and a second dielectric disposed between the first conductive plate and the high voltage node.
1. A microelectronic device, comprising:
a first voltage plate of a first voltage component of the microelectronic device, the first voltage plate having a first end on a first side and a second end on a second, opposite, side;
a second voltage plate of the first voltage component, the second voltage plate having a first end on the first side and a second end on the second side;
a first dielectric layer disposed between the second voltage plate and the first voltage plate;
a first conductive plate disposed between the first dielectric layer and the first voltage plate, wherein the first conductive plate is floating, the first conductive plate has a first end on the first side that extends past the first end of the first voltage plate, the first conductive plate has a second end on the second side that extends past the second end of the first voltage plate, the first end of the second voltage plate is not beyond the first end of the first conductive plate, and the second end of the second voltage plate is not beyond the second end of the first conductive plate; and
a second dielectric layer disposed between the first conductive plate and the first voltage plate.
2. The microelectronic device of claim 1 , wherein the first voltage component is a high voltage capacitor, the second voltage plate is a lower plate of the high voltage capacitor, the first voltage plate is an upper plate of the high voltage capacitor, and the first conductive plate is electrically isolated from the second voltage plate and the first voltage plate.
3. The microelectronic device of claim 1 , wherein the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is different than the second thickness.
4. The microelectronic device of claim 1 , wherein the first dielectric layer comprises a plurality of dielectric layers comprising silicon dioxide-based dielectric material.
5. The microelectronic device of claim 1 , further comprising an isolation break in the first dielectric layer so that the first dielectric layer is not continuous at the isolation break, and the isolation break surrounds the first conductive plate.
6. The microelectronic device of claim 4 , further comprising a second voltage component disposed outside of the isolation break.
7. A capacitor, comprising:
a conductive first capacitor plate disposed above a substrate and having a first edge on a first side and a second end on a second, opposite, side;
a first dielectric layer disposed over the conductive first capacitor plate;
a conductive first floating plate disposed over the first dielectric layer and having a first edge on the first side and a second end on the second side, the conductive first floating plate being electrically isolated from the conductive first capacitor plate;
a second dielectric layer disposed over the conductive first floating plate; and
a conductive second capacitor plate disposed over the second dielectric layer and having a first edge on the first side and a second end on the second side, the conductive second capacitor plate being electrically isolated from the conductive first floating plate, wherein the first edge of the conductive first floating plate extends beyond the first edge of the conductive second capacitor plate and as far as the first edge of the conductive first capacitor plate, and the second edge of the conductive first floating plate extends beyond the second edge of the conductive second capacitor plate and as far as the second edge of the conductive first capacitor plate.
8. The capacitor of claim 7 , wherein the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is different than the second thickness.
9. The capacitor of claim 7 , wherein the first floating plate has a lateral dimension that is different than a lateral dimension of the first capacitor plate.
10. The capacitor of claim 7 , wherein the first dielectric layer comprises a plurality of dielectric layers comprising silicon dioxide-based dielectric material.
11. A microelectronic device, comprising:
a capacitor having:
a first capacitor plate disposed above a substrate, the first capacitor plate having a first lateral dimension in a first direction;
a first dielectric layer disposed over the first capacitor plate;
a conductive first floating plate disposed over the first dielectric layer, the conductive first floating plate having a second lateral dimension in the first direction, the conductive first floating plate being electrically isolated from the first capacitor plate, wherein the first capacitor plate does not extend beyond the conductive first floating plate;
a second dielectric layer disposed over the conductive first floating plate; and
a second capacitor plate disposed over the second dielectric layer, the second capacitor plate having a third lateral dimension in the first direction, wherein the second lateral dimension is greater than the third lateral dimension and at least as long as the first lateral dimension, the second capacitor plate is electrically isolated from the first capacitor plate and from the conductive first floating plate, and the conductive first floating plate extends past the second capacitor plate on two opposite sides along the first lateral direction.
12. The microelectronics device of claim 1 , wherein the first dielectric layer has an interconnect structure and a via embedded therein.
13. The capacitor of claim 7 , wherein the first dielectric layer has an interconnect structure and a via embedded therein.
14. The microelectronics device of claim 11 , wherein the first dielectric layer has an interconnect structure and a via embedded therein.
15. The microelectronics device of claim 1 , wherein the first dielectric layer comprises multiple dielectric layers each with an interconnect structure and a via embedded therein.
16. The capacitor of claim 7 , wherein the first dielectric layer comprises multiple dielectric layers each with an interconnect structure and a via embedded therein.
17. The microelectronics device of claim 11 , wherein the first dielectric layer comprises multiple dielectric layers each with an interconnect structure and a via embedded therein.