IP Library Granted Patent US 11,226,162
Granted Patent B2
US 11,226,162 · App. 15/957,431 · Granted Jan 18, 2022

Heat dissipation device having anisotropic thermally conductive sections and isotropic thermally conductive sections

Inventors: Feras Eid (Chandler, AZ); Adel Elsherbini (Chandler, AZ); Johanna Swan (Scottsdale, AZ)
Assignee: Intel Corporation
F28F3/022F28F13/003H01L23/3677H01L23/3733H01L23/3735
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Quick Facts
Patent No.
US 11,226,162
App. No.
15/957,431
Granted
Jan 18, 2022
Kind
B2
Abstract

A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device. The isotropic thermally conductive section(s) allows heat spreading/removal from hotspots or areas with high-power density and the anisotropic thermally conductive section(s) transfers heat away from the at least one integrated circuit device predominately in a single direction with minimum conduction resistance in areas with uniform power density distribution, while reducing heat transfer in the other directions, thereby reducing thermal cross-talk.

Claims (25)

1. An integrated circuit structure, comprising:

a substrate;

at least one integrated circuit device having a first surface and an opposing second surface, wherein the first surface of the first integrated circuit device is electrically attached to the substrate;

at least one additional integrated circuit device having a first surface and an opposing second surface, wherein the at least one additional integrated circuit is in a stacked configuration with the at least one integrated circuit, wherein the first surface of the at least one additional integrated circuit device is electrically attached to the substrate, and wherein the at least one integrated circuit device is electrically attached to the at least one additional integrated circuit device; and

a heat dissipation device thermally coupled to the second surface of the at least one integrated circuit device, wherein the heat dissipation device comprises at least one isotropic thermally conductive section and at least one anisotropic thermally conductive section and wherein at least a portion of the at least one isotropic thermally conductive section and/or the at least one anisotropic thermally conductive section is positioned vertically over the at least one integrated circuit device.

2. The integrated circuit structure of claim 1 , wherein the at least one anisotropic thermally conductive section comprises a plurality of thermally conductive rods embedded in a thermally insulative material.

3. The integrated circuit structure of claim 2 , wherein the plurality of thermally conductive rods comprises carbon nanorods.

4. The integrated circuit structure of claim 2 , wherein the plurality of thermally conductive rods comprises carbon nanotubes.

5. The integrated circuit structure of claim 1 , wherein the at least one anisotropic thermally conductive section comprises a plurality of thermally conductive sheets embedded in a thermally insulative material.

6. The integrated circuit structure of claim 5 , wherein the plurality of thermally conductive sheets comprises graphene sheets.

7. The integrated circuit structure of claim 1 , wherein the substrate further includes a cavity and wherein the at least one additional integrated circuit is disposed at least partially in the cavity.

8. The integrated circuit structure of claim 1 , wherein the at least one integrated circuit device and the at least one additional integrated circuit device are embedded in a mold material.

9. An electronic system, comprising:

a housing;

a board in the housing;

at least one integrated circuit device having a first surface and an opposing second surface, wherein the first surface of the at least one integrated circuit device is electrically attached to the board;

at least one additional integrated circuit device having a first surface and an opposing second surface, wherein the additional integrated circuit is in a stacked configuration with the at least one integrated circuit, wherein the first surface of the at least one additional integrated circuit device is electrically attached to the substrate, and wherein the at least one integrated circuit device is electrically attached to the at least one additional integrated circuit device; and

a heat dissipation device thermally coupled to the second surface of the at least one integrated circuit device, wherein the heat dissipation device comprises at least one isotropic thermally conductive section and at least one anisotropic thermally conductive section and wherein at least a portion of the at least one isotropic thermally conductive section and/or the at least one anisotropic thermally conductive section is positioned vertically over the at least one integrated circuit device.

10. The electronic system of claim 9 , wherein the at least one anisotropic thermally conductive section comprises a plurality of thermally conductive rods embedded in a thermally insulative material.

11. The electronic system of claim 10 , wherein the plurality of thermally conductive rods comprises carbon nanorods.

12. The electronic system of claim 10 , wherein the plurality of thermally conductive rods comprises carbon nanotubes.

13. The electronic system of claim 9 , wherein the at least one anisotropic thermally conductive section comprises a plurality of thermally conductive sheets embedded in a thermally insulative material.

14. The electronic system of claim 13 , wherein the plurality of thermally conductive sheets comprises graphene sheets.

15. The electronic system of claim 9 , wherein the substrate further includes a cavity and wherein the at least one additional integrated circuit is disposed at least partially in the cavity.

16. The electronic system of claim 9 , wherein the at least one integrated circuit device and the at least one additional integrated circuit device are embedded in a mold material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2018
From: EID, FERAS; ELSHERBINI, ADEL; SWAN, JOHANNA
To: INTEL CORPORATION
Reel/Frame 045673/0933 →
Continuity (1)
Related Publication 20190323785A1 · Oct 24, 2019