IP Library Granted Patent US 11,226,459
Granted Patent B2
US 11,226,459 · App. 16/969,034 · Granted Jan 18, 2022

Integrated photonics device having integrated edge outcouplers

Inventors: Michael J. Bishop (San Carlos, CA); Vijay M. Iyer (Mountain View, CA); Jason S. Pelc (Sunnyvale, CA); Mario J. Costello (San Jose, CA)
G02B6/4268G01N21/4785G01N21/49G02B6/4214G02B6/4251
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Quick Facts
Patent No.
US 11,226,459
App. No.
16/969,034
Granted
Jan 18, 2022
Kind
B2
Abstract

Described herein is an integrated photonics device including a light emitter, integrated edge outcoupler(s), optics, and a detector array. The device can include a hermetically sealed enclosure. The hermetic seal can reduce the amount of moisture and/or contamination that may affect the measurement, analysis, and/or the function of the individual components within the sealed enclosure. Additionally or alternatively, the hermetic seal can be used to protect the components within the enclosure from environmental contamination induced during the manufacturing, packaging, and/or shipping process. The outcoupler(s) can be formed by creating one or more pockets in the layers of a die. Outcoupler material can be formed in the pocket and, optionally, subsequent layers can be deposited on top. The edge of the die can be polished until a targeted polish plane is achieved. Once the outcoupler is formed, the die can be flipped over and other components can be formed.

Claims (65)

1. An integrated photonics device including:

a supporting layer including a first side and a second side;

one or more windows located at a system interface of the integrated photonics device;

optics configured to redirect, focus, and/or collimate incident light to or from the one or more windows;

one or more edge outcouplers configured to redirect light towards at least some of the optics;

one or more light emitters configured to emit light in response to first signals, where the emitted light is incident on the one or more edge outcouplers;

a plurality of first layers deposited on the first side of the supporting layer, wherein the plurality of first layers is configured to route the first signals from a controller to the one or more light emitters;

one or more detectors configured to detect return light and generate second signals indicative of the detected return light, wherein the detected return light includes at least a portion of the emitted light;

a plurality of second layers deposited on the second side of the supporting layer, wherein the plurality of second layers is configured to route second signals from the one or more detectors to the controller or a processor; and

the controller or the processor configured to determine one or more sample properties based on the second signals.

2. The integrated photonics device of claim 1 , further comprising:

a frame connected to the supporting layer, wherein the frame is configured to create a hermetic seal around at least the one or more detectors and at least some of the optics.

3. The integrated photonics device of claim 2 , further comprising:

one or more traces electrically connected to the one or more second layers, wherein the one or more traces are configured to route the second signals to a location outside of the hermetic seal.

4. The integrated photonics device of claim 1 , further comprising:

one or more thermal slugs configured to relocate heat from one location to another, the one or more thermal slugs thermally coupled to the supporting layer and the one or more windows.

5. The integrated photonics device of claim 4 , wherein the one or more thermal slugs are located around the one or more optics.

6. The integrated photonics device of claim 4 , further comprising:

one or more solder connections configured to connect the one or more thermal slugs to the supporting layer, wherein the one or more solder connections are located in locations corresponding to the one or more light emitters.

7. The integrated photonics device of claim 1 , wherein:

the one or more edge outcouplers includes an outcoupler material, the outcoupler material including amorphous silicon,

the supporting layer includes silicon, and

the plurality of first layers includes silicon and silicon dioxide.

8. The integrated photonics device of claim 1 , wherein the plurality of first layers includes one or more of insulating layer(s) and conductive layer(s),

at least some of the plurality of first layers including a plurality of fiducials, wherein at least two of the plurality of fiducials are offset relative to one another, the offset based on a target polishing plane.

9. The integrated photonics device of claim 8 , further comprising:

a plurality of second fiducials, wherein the plurality of second fiducials is oriented along a different direction than the plurality of fiducials.

10. The integrated photonics device of claim 1 , wherein the optics are one-layer optics.

11. A method for determining one or more properties of a sample using an integrated photonics device, the method comprising:

emitting light towards one or more waveguides located on a first side of a supporting layer;

propagating the emitted light using the one or more waveguides to one or more edge outcouplers, the one or more waveguides formed from at least some of a plurality of first layers;

redirecting the emitted light using the one or more edge outcouplers towards optics;

redirecting, focusing, and/or collimating the redirected light using the optics towards one or more windows of the integrated photonics device;

receiving return light from the one or more windows by one or more detectors located on a second side of the supporting layer;

generating second signals indicative of the return light using the one or more detectors; and

determining the one or more properties of the sample based on the second signals.

12. The method of claim 11 , further comprising:

creating a hermetic seal around at least the one or more detectors and the one or more windows.

13. The method of claim 12 , further comprising:

routing the second signals from the one or more detectors to a controller located outside of the hermetic seal.

14. The method of claim 11 , further comprising:

routing first signals from a controller using one or more of an interposer and bonding bumps; and

transmitting first signals to the one or more light emitters, the first signals associated with the emitted light from the one or more light emitters.

15. The method of claim 11 , further comprising:

relocating heat from the one or more light emitters to the one or more windows using one or more thermal slugs.

16. A method for forming an integrated photonics device, the method comprising:

providing a wafer, the wafer including a supporting layer and a plurality of first layers on a first side of the supporting layer; and

forming one or more integrated edge outcouplers including:

forming one or more pockets by etching the plurality of first layers,

forming a plurality of second layers on a second side of the supporting layer,

forming a detector array on a second side of the supporting layer,

growing outcoupler material in the one or more pockets, and

polishing at least one edge of wafer along a target polish plane, wherein the polish exposes at a least a portion of the outcoupler material.

17. The method of claim 16 , wherein forming the one or more integrated edge outcouplers further comprises:

depositing additional material on top of the outcoupler material prior to the polishing.

18. The method of claim 16 , wherein forming the one or more integrated edge outcouplers further comprises:

depositing a plurality of fiducials in the plurality of layers such that the plurality of fiducials is offset with respect to one another to form the target polish plane.

19. The method of claim 16 , further comprising:

connecting a frame to the supporting layer; and

creating a hermetic seal using the frame.

20. The method of claim 16 , further comprising:

forming one or more light emitters on the first side of the supporting layer;

forming one or more solder connections in locations corresponding to the one or more light emitters;

forming one or more thermal slugs; and

thermally coupling the one or more thermal slugs to the supporting layer using the one or more solder connections.

Continuity (2)
Provisional Application 62630018 · Feb 13, 2018
Related Publication 20210033805A1 · Feb 4, 2021
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