IP Library Granted Patent US 11,226,740
Granted Patent B2
US 11,226,740 · App. 16/669,160 · Granted Jan 18, 2022

Selectively performing inline compression based on data entropy

Inventors: Uri Shabi (Tel Mond, IL); Alexei Kabishcer (Ramat Gan, IL)
Assignee: EMC IP Holding Company LLC
G06F3/0608G06F3/064G06F3/0659G06F3/0673G06F9/30043G06F9/30079
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Quick Facts
Patent No.
US 11,226,740
App. No.
16/669,160
Filed
Oct 30, 2019
Granted
Jan 18, 2022
Kind
B2
Art Unit
2181
USPC
711/154
Abstract

A technique for managing data storage obtains a batch of chunks of data. The technique generates, using multiple pipelined instructions operating on the batch, a measure of data entropy for each of the chunks in the batch. The technique selectively compresses chunks in the batch based at least in part on the measures of data entropy generated for the respective chunks.

Claims (34)

1. A method of managing data storage in a computerized system, the method comprising:

obtaining a batch of chunks, the batch including a plurality of chunks of data;

generating, using multiple pipelined instructions operating on the batch, a measure of data entropy for each of the plurality of chunks in the batch; and

selectively compressing chunks of the plurality of chunks based at least in part on the measures of data entropy generated for the respective chunks,

wherein the multiple pipelined instructions include pipelined processor instructions of a single CPU (central processing unit), and wherein the pipelined processor instructions include N load instructions from a cache, wherein N is at least as large as a latency in accessing the cache by the CPU as measured in clock cycles of the CPU.

2. The method of claim 1 , wherein the chunks within the batch are of equal size.

3. The method of claim 1 , wherein pipelined instructions include load instructions for loading respective data elements from a cache, and wherein a number of the plurality of chunks is at least as great as a number of clock cycles required for the CPU to load each data element from the cache.

4. The method of claim 3 , further comprising executing the load instructions sequentially during respective clock cycles of the CPU.

5. The method of claim 3 , wherein the data elements represent counts of symbols occurring in the chunks.

6. The method of claim 5 , wherein the data elements include a plurality of data elements for each chunk.

7. The method of claim 6 , wherein the plurality of data elements for each chunk includes a data element for each symbol allowed to occur in the chunk.

8. The method of claim 3 , wherein each of the data elements has a respective address location in the cache which is not shared with any other of the data elements.

9. The method of claim 1 , further comprising providing a look up table (LUT) that associates (i) counts of symbol occurrences with (ii) entropy components corresponding to the respective counts.

10. The method of claim 9 , wherein the entropy components in the LUT are integer values.

11. The method of claim 10 , wherein generating the measure of data entropy for a chunk includes (i) obtaining a set of entropy components from the LUT based on counts of symbols appearing in the chunk and (ii) generating a sum of the obtained entropy components.

12. The method of claim 11 , wherein generating the sum of entropy components includes adding entropy components across all unique symbols in the chunk.

13. The method of claim 11 , wherein generating the sum of entropy components includes adding entropy components across fewer than all unique symbols in the chunk.

14. The method of claim 13 , wherein the symbols have a numerical sequence, and wherein adding entropy components across fewer than all unique symbols in the chunk includes adding entropy components from every Nth symbol in the sequence, where N is an integer greater than one, and excluding from the sum other symbols in the sequence.

15. A computerized system, comprising control circuitry that includes a set of processing units coupled to memory, the control circuitry constructed and arranged to:

obtain a batch of chunks, the batch including a plurality of chunks of data;

generate, using multiple pipelined instructions operating on the batch, a measure of data entropy for each of the plurality of chunks in the batch; and

selectively compress chunks of the plurality of chunks based at least in part on the measures of data entropy generated for the respective chunks,

wherein the multiple pipelined instructions include pipelined processor instructions of a single CPU (central processing unit), and wherein the pipelined processor instructions include N load instructions from a cache, wherein N is at least as large as a latency in accessing the cache by the CPU as measured in clock cycles of the CPU.

16. The system of claim 15 , wherein the chunks within the batch are of equal size.

17. A computer program product including a set of non-transitory, computer-readable media having instructions which, when executed by control circuitry of a computerized system, cause the control circuitry to perform a method of managing data storage, the method comprising:

obtaining a batch of chunks, the batch including a plurality of chunks of data;

generating, using multiple pipelined instructions operating on the batch, a measure of data entropy for each of the plurality of chunks in the batch; and

selectively compressing chunks of the plurality of chunks based at least in part on the measures of data entropy generated for the respective chunks,

wherein the multiple pipelined instructions include pipelined processor instructions of a single CPU (central processing unit), and wherein the pipelined processor instructions include N load instructions from a cache, wherein N is at least as large as a latency in accessing the cache by the CPU as measured in clock cycles of the CPU.

18. The method of claim 1 , wherein the CPU avoids inactivity while waiting for results of a first load instruction to arrive from the cache by performing successive load instructions of the pipelined instructions.

19. The computerized system of claim 15 , wherein the CPU avoids inactivity while waiting for results of a first load instruction to arrive from the cache by performing successive load instructions of the pipelined instructions.

20. The computerized system of claim 15 , wherein the control circuitry is further constructed and arranged to provide a look up table (LUT) that associates (i) counts of symbol occurrences with (ii) entropy components corresponding to the respective counts.

21. The computer program product of claim 17 , wherein the CPU avoids inactivity while waiting for results of a first load instruction to arrive from the cache by performing successive load instructions of the pipelined instructions.

22. The computer program product of claim 17 , wherein the method further comprises providing a look up table (LUT) that associates (i) counts of symbol occurrences with (ii) entropy components corresponding to the respective counts.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (051302/0528) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.); SECUREWORKS CORP.
Reel/Frame 060438/0593 →
RELEASE OF SECURITY INTEREST AT REEL 051449 FRAME 0728 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.; SECUREWORKS CORP.; EMC CORPORATION
Reel/Frame 058002/0010 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Dec 31, 2019
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.; SECUREWORKS CORP.; EMC CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 051449/0728 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Dec 16, 2019
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.; SECUREWORKS CORP.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 051302/0528 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2019
From: SHABI, URI; KABISHCER, ALEXEI
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 051164/0117 →
Continuity (1)
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