Tracking events of interest to mitigate attacks

1. A computing device comprising:

a comparator coupled to an I/O pin of the computing device for detecting repetitive input signals;

a storage unit coupled to the comparator for storing a representative input signal, wherein the comparator compares an input received via the I/O pin to the representative input signal stored in the storage unit to determine whether the input matches the representative input signal, and wherein the representative input signal stored in the storage unit is a prior incoming signal received via the I/O pin; and

a counter coupled to receive an output of the comparator, wherein the counter increments upon the comparator indicating that the input matches the representative input signal indicating a repetitive input signal, wherein an output of the counter is coupled to a computation engine to provide a limit-exceeded signal to the computation engine when a value at the counter exceeds a predetermined level of acceptability for repetitive input signals, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter.

2. The computing device of claim 1 , wherein the value at the counter that exceeds the predetermined level of acceptability for repetitive input signals occurs when an output of the volatile counter reaches or exceeds a threshold, wherein when the output of the volatile counter reaches or exceeds the threshold, the limit-exceeded signal is provided to the computation engine.

3. The computing device of claim 1 , wherein the value at the counter that exceeds the predetermined level of acceptability for repetitive input signals occurs when a total count from the volatile counter and the nonvolatile storage reaches or exceeds a threshold, wherein when the total count from the volatile counter and the nonvolatile storage reaches or exceeds the threshold, the limit-exceeded signal is provided to the computation engine.

4. The computing device of claim 1 , wherein the limit-exceeded signal is used by the computation engine to initiate a countermeasure response.

5. The computing device of claim 1 , further comprising:

a backup power source coupled to the volatile counter; and

readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events.

6. The computing device of claim 1 , wherein the computation engine comprises a cryptography engine.

7. The computing device of claim 1 , further comprising:

a plurality of comparators; and

a corresponding plurality of storage units.

8. The computing device of claim 7 , further comprising:

a corresponding plurality of volatile counters coupled to the plurality of comparators.

9. The computing device of claim 8 , wherein at least two volatile counters are coupled to the nonvolatile storage.

10. The computing device of claim 9 , wherein the nonvolatile storage separately stores bits corresponding to each top volatile count number of events identified by the at least two volatile counters such that a total count can be performed separately.

11. The computing device of claim 8 , further comprising:

a corresponding plurality of nonvolatile storage for each volatile counter of the plurality of volatile counters.

12. The computing device of claim 1 , wherein the representative input signal stored in the storage unit comprises digital bits.

13. The computing device of claim 1 , wherein the representative input signal comprises plain text or cipher text of an information cycle of a smart card transaction.