Magnetoresistive random-access memory
In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.
1. A magnetoresistive random-access memory (MRAM), comprising:
a first bit line;
a second bit line; and
a first unit cell, comprising:
a first non-volatile storage unit, comprising:
a first end coupled to the first bit line; and
a second end;
a second non-volatile storage unit, comprising:
a first end coupled to the second bit line; and
a second end;
a first N-type transistor, comprising:
a first end coupled to the second end of the first non-volatile storage unit;
a second end; and
a control end;
a second N-type transistor, comprising:
a first end coupled to the second end of the second non-volatile storage unit;
a second end; and
a control end;
a third N-type transistor, comprising:
a first end coupled to the first end of the first N-type transistor;
a second end coupled to the first end of the second N-type transistor; and
a control end;
a first P-type transistor, comprising:
a first end coupled to the second end of the first N-type transistor;
a second end coupled to the first end of the first N-type transistor; and
a control end;
a second P-type transistor, comprising:
a first end coupled to the second end of the second N-type transistor;
a second end coupled to the first end of the second N-type transistor; and
a control end; and
a third P-type transistor, comprising:
a first end coupled to the second end of the third N-type transistor;
a second end coupled to the first end of the third N-type transistor; and
a control end.
2. The MRAM of claim 1 , wherein:
the control end of the first N-type transistor, the control end of the second N-type transistor and the control end of the third N-type transistor are coupled to a first word line; and
the control end of the first P-type transistor, the control end of the second P-type transistor and the control end of the third P-type transistor are coupled to a second word line.
3. The MRAM of claim 1 , further comprising a second unit cell which comprises:
a third non-volatile storage unit, comprising:
a first end coupled to the first bit line; and
a second end;
a fourth non-volatile storage unit, comprising:
a first end coupled to the second bit line; and
a second end;
a fourth N-type transistor, comprising:
a first end coupled to the second end of the third non-volatile storage unit;
a second end; and
a control end;
a fifth N-type transistor, comprising:
a first end coupled to the second end of the fourth non-volatile storage unit;
a second end; and
a control end;
a sixth N-type transistor, comprising:
a first end coupled to the first end of the fourth N-type transistor;
a second end coupled to the first end of the fifth N-type transistor; and
a control end;
a fourth P-type transistor, comprising:
a first end coupled to the second end of the fourth N-type transistor;
a second end coupled to the first end of the fourth N-type transistor; and
a control end;
a fifth P-type transistor, comprising:
a first end coupled to the second end of the fifth N-type transistor;
a second end coupled to the first end of the fifth N-type transistor; and
a control end; and
a sixth P-type transistor, comprising:
a first end coupled to the second end of the sixth N-type transistor;
a second end coupled to the first end of the sixth N-type transistor; and
a control end.
4. The MRAM of claim 3 , wherein:
the control end of the first N-type transistor, the control end of the second N-type transistor, the control end of the third N-type transistor, the control end of the fourth N-type transistor, the control end of the fifth N-type transistor and the control end of the sixth N-type transistor are coupled to a first word line; and
the control end of the first P-type transistor, the control end of the second P-type transistor, the control end of the third P-type transistor, the control end of the fourth P-type transistor, the control end of the fifth P-type transistor and the control end of the sixth P-type transistor are coupled to a second word line.
5. The MRAM of claim 3 , wherein:
the second end of the first N-type transistor and the second end of the second N-type transistor are coupled to a first source line; and
the second end of the fourth N-type transistor and the second end of the fifth N-type transistor are coupled to a second source line.
6. The MRAM of claim 1 , further comprising:
a third bit line;
a fourth bit line; and
a third unit cell, comprising:
a fifth non-volatile storage unit, comprising:
a first end coupled to the third bit line; and
a second end;
a sixth non-volatile storage unit, comprising:
a first end coupled to the fourth bit line; and
a second end;
a seventh N-type transistor, comprising:
a first end coupled to the second end of the fifth non-volatile storage unit;
a second end; and
a control end;
an eighth N-type transistor, comprising:
a first end coupled to the second end of the sixth non-volatile storage unit;
a second end; and
a control end;
a ninth N-type transistor, comprising:
a first end coupled to the first end of the seventh N-type transistor;
a second end coupled to the first end of the eighth N-type transistor; and
a control end;
a seventh P-type transistor, comprising:
a first end coupled to the second end of the seventh N-type transistor;
a second end coupled to the first end of the seventh N-type transistor; and
a control end;
an eighth P-type transistor, comprising:
a first end coupled to the second end of the eighth N-type transistor;
a second end coupled to the first end of the eighth N-type transistor; and
a control end; and
a ninth P-type transistor, comprising:
a first end coupled to the second end of the ninth N-type transistor;
a second end coupled to the first end of the ninth N-type transistor; and
a control end.
7. The MRAM of claim 6 , wherein:
the control end of the first N-type transistor, the control end of the second N-type transistor, the control end of the third N-type transistor, the control end of the seventh N-type transistor, the control end of the eighth N-type transistor and the control end of the ninth N-type transistor are coupled to a first word line; and
the control end of the first P-type transistor, the control end of the second P-type transistor, the control end of the third P-type transistor, the control end of the seventh P-type transistor, the control end of the eighth P-type transistor and the control end of the ninth P-type transistor are coupled to a second word line.
8. The MRAM of claim 6 , wherein:
the second end of the first N-type transistor, the second end of the second N-type transistor, the second end of the seventh N-type transistor and the second end of the eighth N-type transistor are coupled to a source line.
9. A magnetoresistive random-access memory (MRAM), comprising:
an N-type doping region formed in a substrate;
a P-type doping region formed in the substrate;
a poly-silicon layer formed on the substrate;
a first metal layer formed on the substrate;
a second metal layer formed above the first metal layer;
a first non-volatile storage unit disposed above the second metal layer and located on a first reference line;
a second non-volatile storage unit disposed above the second metal layer and located on a second reference line parallel to the first reference line;
a third metal layer formed above the first non-volatile storage unit and the second non-volatile storage unit; and
a fourth metal layer formed above the third metal layer.
10. The MRAM of claim 9 , further comprising:
an N-type transistor, comprising:
a first end formed in the N-type doping region;
a second end formed in the N-type doping region; and
a control end formed on the substrate at a location corresponding to a first channel;
a P-type transistor, comprising:
a first end formed in the P-type doping region;
a second end formed in the P-type doping region; and
a control end formed on the substrate at a location corresponding to a second channel;
a word line formed in the first metal layer;
a source line formed in the second metal layer;
a first bit line formed in the third metal layer and the fourth metal layer; and
a second bit line formed in the third metal layer and the fourth metal layer.
11. The MRAM of claim 10 , further comprising:
a first via formed between the third metal layer and first non-volatile storage unit for electrically connecting the first bit line to the first non-volatile storage unit; and
a second via formed between the third metal layer and second non-volatile storage unit for electrically connecting the second bit line to the second non-volatile storage unit.