Thin film transistor substrate and method of fabricating same

1. A method of fabricating a thin film transistor substrate, comprising steps of:

S1, providing a substrate, sequentially forming a light shielding layer, a buffer layer, and an active layer on the substrate;

S2, forming a gate insulating layer on the active layer, wherein the gate insulating layer comprises a stacked structure comprising a first insulating layer and a second insulating layer, a thickness of the first insulating layer is not less than a thickness of the second insulating layer, and the second insulating layer is disposed on the first insulating layer;

S3, sequentially forming a metal layer and a photoresist layer on the gate insulating layer;

S4, etching the metal layer by using the photoresist layer as an occlusion to obtain a gate layer, and removing a portion of the metal layer that is not blocked by the photoresist layer;

S5, etching the gate insulating layer by self-aligning the gate layer, and performing a conductor treatment, wherein the active layer not blocked by the gate insulating layer forms a conductor layer;

S6, after the gate insulating layer is etched and the conductor treatment is completed, the photoresist layer is stripped;

S7, forming an interlayer insulating layer on the gate layer;

S8, opening at least one hole in the interlayer insulating layer and the buffer layer to form at least one via hole;

S9, forming a source/drain metal layer in the at least one via hole; and

S10, forming a passivation layer on the source/drain metal layer;

wherein the at least one via hole is formed by a yellow light process, the at least one via hole comprises a first via hole, a second via hole, and a third via hole, the first via hole is connected to a first conductor layer through the interlayer insulating layer, the second via hole is connected to a second conductor layer through the interlayer insulating layer, and the third via hole is connected to the light shielding layer through the interlayer insulating layer and the buffer layer sequentially.

2. The method according to claim 1 , wherein the source/drain metal layer comprises a source metal layer and a drain metal layer, the source metal layer is formed in the second via hole and the third via hole, and the drain metal layer is formed in the first via hole.

3. The method according to claim 1 , wherein the light shielding layer, the gate layer, and the source/drain metal layer are made of the same material which is at least one of molybdenum, aluminum, copper, and titanium, a thickness of the light shielding layer ranges between 500 angstroms and 2000 angstroms, the gate layer and the source/drain metal layer have the same thickness ranging between 2000 angstroms and 8000 angstroms, material of the active layer comprises a metal oxide semiconductor material, and a thickness of the active layer ranges between 100 angstroms and 1000 angstroms.

4. The method according to claim 1 , wherein the buffer layer, the interlayer insulating layer, and the passivation layer are made of the same material which is at least one of silicon oxide and silicon nitride, a thickness of the interlayer insulating layer ranges between 2000 angstroms and 10000 angstroms, and the buffer layer and the passivation layer have the same thickness ranging between 1000 angstroms and 5000 angstroms.