Networks and hierarchical routing fabrics with heterogeneous memory structures for scalable event-driven computing systems
Among other aspects, the present invention relates to a network comprising a plurality of interconnected core circuits ( 10 ) particularly arranged on several units ( 6 ), wherein each core circuit ( 10 ) comprises: an electronic array ( 8, 9 ) comprising a plurality of computing nodes ( 90 ) and a plurality of memory circuits ( 80 ) which is configured to receive incoming events, wherein each computing node ( 90 ) is configured to generate an event comprising a data packet when incoming events received by the respective computing node ( 90 ) satisfy a pre-defined criterion, and a circuit which is configured to append destination address and additional source information, particularly source core ID, to the respective data packet, and a local first router (R 1 ) for providing intra-core connectivity and/or delivering events to intermediate level second router (R 2 ) for inter-core connectivity and to higher level third router (R 3 ) for inter-unit connectivity, and a broadcast driver ( 7 ) for broadcasting incoming events to all the memory circuits ( 80 ) in the core circuit ( 10 ) in parallel.
1. A neural network circuit, which comprises a plurality of tiles/chips ( 6 ); the tiles/chips ( 6 ) comprising a plurality of cores ( 10 ), the core ( 10 ) comprising at least one neuron circuit ( 90 ) that simulates biological neuron and at least one synapse circuit ( 80 ) that simulates synapse;
the neuron circuit ( 90 ) integrates multiple events received and accepted by the corresponding synapse circuits ( 80 ), and generates a spike event when the integrated signal crosses the trigger threshold;
its characteristics are:
the core ( 10 ) also includes: a core router R 1 for providing circuit connectivity within the core;
the tile/chip ( 6 ) further includes: a chip router R 2 for providing connectivity between the cores and a mesh router R 3 for providing connectivity between the tiles/chips ( 6 );
wherein, the core router R 1 transmits or/and receives events to the chip router R 2 , and the chip router R 2 transmits or/and receives events to the mesh router R 3 ;
on one tile/chip ( 6 ), the core router R 1 , the chip router R 2 and the mesh router R 3 form a tree structure;
the mesh router R 3 is arranged in a two-dimensional mesh; each tile/chip ( 6 ) has one mesh router R 3 , and the mesh router R 3 interconnects the tree structure in the two-dimensional mesh;
a broadcast driver ( 7 ), which is configured to broadcast to synapse array ( 8 ) through the broadcast driver ( 7 ) after the core router R 1 receives an event, and the synapse array ( 8 ) has a plurality of said synapse circuits ( 80 ).
2. The neural network circuit according to claim 1 , wherein:
when the neuron circuit ( 90 ) generates a spike event, the address of the spike event is sent to the core router R 1 ;
the core ( 10 ) further includes a destination LUT ( 3 ), which is configured to store the destination of the spike event and is accessible by the core router R 1 .
3. The neural network circuit according to claim 2 , wherein:
the core router R 1 determines whether send the event back to said core ( 10 ) or append to the event packet a digital code representing the destination for this event.
4. The neural network circuit according to claim 3 , wherein:
the digital code representing the destination for this event includes 6-bits for chip/tile shifting of dx and dy, 2-bits for virtual source core ID and 4-bits for within-chip destinations.
5. The neural network circuit according to claim 4 , wherein:
the digital code includes codes dx and dy for shifting;
after the mesh router R 3 receives an event from the chip router R 2 , the mesh router R 3 checks the shift number dx in the x direction firstly, and the shift direction is determined according to the sign of dx, dx is reduced by 1, and the event is transmitted to the correct direction;
if the shift number dx in the x direction is 0, the mesh router R 3 checks the shift number dy in the y direction, and according to the sign of dy determines the shift direction, dy is reduced by 1, and the event is transmitted to the correct direction;
thus, the event travels along the mesh until both dx and dy are 0.
6. The neural network circuit according to claim 1 , wherein:
the chip router R 2 has three levels/layers branches or only one level/layer branches.
7. The neural network circuit according to claim 1 , wherein:
CAM word is used as synapse circuit ( 80 ) for storing the address of the source neuron circuit ( 90 ) it is connected to, the synapse type, and its synaptic efficacy.
8. The neural network circuit according to claim 7 , wherein:
the event arriving at one core are broadcasted to the whole core by the broadcast driver ( 7 );
each CAM compares the event on the broadcast bus with stored address, the ones for which the address matches the broadcasted event will raise a match state and generate appropriate post-synaptic current.
9. The neural network circuit according to claim 1 , wherein:
the core ( 10 ) includes: SRAM memory ( 2 ) for storing destination LUT ( 3 ).
10. The neural network circuit according to claim 1 , wherein:
the neural network circuit further includes router memory ( 32 ) accessing for the chip router R 2 .
11. The neural network circuit according to claim 10 , wherein:
router memories are programmed such that events climb the tree through chip router R 2 at different levels as much as needed to reach any destination cores ( 10 ) within the chip ( 6 ).
12. The neural network circuit according to claim 11 , wherein:
if the target of an event resides on a core ( 10 ) of a different chip ( 6 ), the event is sent through all the layers up to the mesh router R 3 , which will further process and deliver it along the appropriate directions in the mesh.
13. The neural network circuit according to claim 1 , wherein:
a plurality of chip routers R 2 constitute a tree-like router, and the tree-like router has multiple levels, and each level includes at least one dedicated chip router R 2 , which is used for core ( 10 ) communication within the level and is used for communication in the tree structure in sending events to/receiving events from other levels.
14. A router fabric equipment, which applied to network interconnection within and between tiles/chips ( 6 ) with multiple cores ( 10 );
the core ( 10 ) includes at least one neuron circuit ( 90 ) that simulates biological neuron and at least one synapse circuit ( 80 ) that simulates synapse;
its characteristics are:
the core ( 10 ) also includes: a core router R 1 for providing circuit connectivity within the core;
the tile/chip ( 6 ) further includes: a chip router R 2 for providing connectivity between the cores and a mesh router R 3 for providing connectivity between the tiles/chips ( 6 );
wherein, the core router R 1 transmits or/and receives events to the chip router R 2 , and the chip router R 2 transmits or/and receives events to the mesh router R 3 ;
on one tile/chip ( 6 ), the core router R 1 , the chip router R 2 and the mesh router R 3 form a tree structure;
the mesh router R 3 is arranged in a two-dimensional mesh; each tile/chip ( 6 ) has one mesh router R 3 , and the mesh router R 3 interconnects the tree structure in the two-dimensional mesh;
a broadcast driver ( 7 ), which is configured to broadcast to synapse array ( 8 ) through the broadcast driver ( 7 ) after the core router R 1 receives an event, and the synapse array ( 8 ) has a plurality of said synapse circuits ( 80 ).
15. The router fabric equipment according to claim 14 , wherein:
CAM word is used as synapse circuit ( 80 ) for storing the address of the source neuron circuit ( 90 ) it is connected to, the synapse type, and its synaptic efficacy.
16. The router fabric equipment according to claim 15 , wherein:
the event arriving at one core are broadcasted to the whole core by the broadcast driver ( 7 );
each CAM compares the event on the broadcast bus with stored address, the ones for which the address matches the broadcasted event will raise a match state and generate appropriate post-synaptic current.
17. The router fabric equipment according to claim 14 , wherein:
router memories are programmed such that events climb the tree through chip router R 2 at different levels as much as needed to reach any destination cores ( 10 ) within the chip ( 6 ).
18. The router fabric equipment according to claim 17 , wherein:
if the target of an event resides on a core ( 10 ) of a different chip ( 6 ), the event is sent through all the layers up to the mesh router R 3 , which will further process and deliver it along the appropriate directions in the mesh.
19. The router fabric equipment according to claim 14 , wherein:
a plurality of chip routers R 2 constitute a tree-like router, and the tree-like router has multiple levels, and each level includes at least one dedicated chip router R 2 , which is used for core ( 10 ) communication within the level and is used for communication in the tree structure in sending events to/receiving events from other levels.
20. The router fabric equipment according to claim 14 , wherein:
when the neuron circuit ( 90 ) generates a spike event, the address of the spike event is sent to the core router R 1 ;
the core ( 10 ) further includes a destination LUT ( 3 ), which is configured to store the destination of the spike event and is accessible by the core router R 1 ;
the core router R 1 determines whether send the event back to said core ( 10 ) or append to the event packet a digital code representing the destination for this event;
the digital code includes codes dx and dy for shifting;
after the mesh router R 3 receives an event from the chip router R 2 , the mesh router R 3 checks the shift number dx in the x direction firstly, and the shift direction is determined according to the sign of dx, dx is reduced by 1, and the event is transmitted to the correct direction;
if the shift number dx in the x direction is 0, the mesh router R 3 checks the shift number dy in the y direction, and according to the sign of dy determines the shift direction, dy is reduced by 1, and the event is transmitted to the correct direction;
thus, the event travels along the mesh until both dx and dy are 0.