Solid-state imaging device and imaging device with combined dynamic vision sensor and imaging functions

1. An imaging device, comprising:

a pixel array unit, wherein the pixel array unit includes:

a plurality of pixels; and

an isolation structure, wherein each pixel in the plurality of pixels is separated from one or more neighboring pixels in the plurality of pixels by the isolation structure, and wherein each pixel includes:

a photoelectric conversion region;

a first transfer transistor;

a second transfer transistor;

a first readout circuit selectively coupled to the photoelectric conversion region by the first transfer transistor; and

a second readout circuit selectively coupled to the photoelectric conversion region by the second transfer transistor,

wherein, for each pixel, all transistor components of the first readout circuit are laid out in a first half of the pixel in a plan view, and all transistor components of the second readout circuit are laid out in a second half of the pixel in the plan view,

wherein the first readout circuit includes a floating diffusion layer, an amplification transistor, a selection transistor, and a reset transistor, and

wherein the second readout circuit includes a first log transistor and a first amplification transistor.

2. The imaging device of claim 1 , wherein the second readout circuit is an address event detection readout circuit.

3. The imaging device of claim 2 , wherein the first readout circuit is an imaging signal generation readout circuit.

4. The imaging device of claim 3 , wherein the pixel array unit includes a plurality of pixel groups, wherein each pixel within a first pixel group in the plurality of pixel groups is isolated from other pixels in the first pixel group.

5. The imaging device of claim 4 , wherein the isolation structure is a dielectric structure.

6. The imaging device of claim 5 , wherein the dielectric structure surrounds each of the pixels within the first pixel group.

7. The imaging device of claim 6 , wherein the dielectric structure is a full-thickness dielectric trench.

8. The imaging device of claim 4 , wherein each pixel group further includes a first unit pixel, a second unit pixel, a third unit pixel, and a fourth unit pixel, and wherein the first, second, third, and fourth unit pixels are disposed in a 2×2 array.

9. The imaging device of claim 8 , wherein the isolation structure defines a pixel area for each of the unit pixels, and wherein circuit elements of each unit pixel are separated from circuit elements of any neighboring unit pixel in the pixel array unit by the isolation structure.

10. The imaging device of claim 1 , wherein the second readout circuit includes a current to voltage conversion unit and a subtractor, the current to voltage conversion unit including the first log transistor and the first amplification transistor.

11. The imaging device of claim 1 , wherein the second readout circuit further includes a second log transistor and a second amplification transistor.

12. The imaging device of claim 1 , wherein the photoelectric conversion region includes a plurality of sides in a plan view, wherein a gate of the first transfer transistor is located along a first side of the photoelectric conversion region, and wherein a gate of the second transfer transistor is located along a second side of the photoelectric conversion region.

13. The imaging device of claim 1 , wherein the first isolation structure is entirely a full thickness trench isolation structure.

14. An imaging device, comprising:

a pixel array unit, wherein the pixel array unit includes:

a plurality of pixels; and

an isolation structure, wherein each pixel in the plurality of pixels is separated from one or more neighboring pixels in the plurality of pixels by the isolation structure, and wherein each pixel includes:

a photoelectric conversion region;

a first transfer transistor;

a second transfer transistor;

a first readout circuit selectively coupled to the photoelectric conversion region by the first transfer transistor; and

a second readout circuit selectively coupled to the photoelectric conversion region by the second transfer transistor, wherein the first transfer transistor includes a first transfer gate that is one of an N-type transfer gate or a P-type transfer gate, and wherein the second transfer transistor includes a second transfer gate that is a the other one of the N-type transfer gate or the P-type transfer gate.

15. The imaging device of claim 14 , wherein the photoelectric conversion region of at least a first pixel included in the plurality of pixels is selectively connected to the first and second readout circuits simultaneously.

16. The imaging device of claim 14 , further comprising:

a joint signal line, wherein the joint signal line electrically connects the first transfer gate to the second transfer gate.

17. The imaging device of claim 14 , wherein the first readout circuit includes the first transfer transistor, an amplification transistor, a selection transistor, and a reset transistor.

18. An electronic apparatus, comprising:

an imaging lens; and

a solid-state imaging device, including:

a pixel array unit, wherein the pixel array unit includes:

a plurality of pixels;

an isolation structure, wherein each pixel in the plurality of pixels is separated from one or more neighboring pixels in the plurality of pixels by the isolation structure, and wherein each pixel includes:

a photoelectric conversion region;

a first transfer transistor;

a second transfer transistor;

a first readout circuit selectively coupled to the photoelectric conversion region by the first transfer transistor; and

a second readout circuit selectively coupled to the photoelectric conversion region by the second transfer transistor; and

a control unit, wherein the control unit controls operation of the solid-state imaging device,

wherein a gate of the first transfer transistor is located along a first side of the photoelectric conversion region in a plan view, and wherein a gate of the second transfer transistor is located along a second side of the photoelectric conversion region in the plan view, the second side being opposite the first side,

wherein the first readout circuit includes a floating diffusion layer, an amplification transistor, a selection transistor, and a reset transistor, and

wherein the second readout circuit includes a current to voltage conversion unit and a subtractor.