Customizable backup and restore from nonvolatile logic array
Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.
1. A computing apparatus, comprising:
a system clock;
a circuit comprising:
a non-volatile logic element array; and
a plurality of volatile storage elements coupled to the non-volatile logic element array; and
at least one non-volatile logic controller coupled to the non-volatile logic element array, the at least one non-volatile logic controller configured to:
receive input signals, wherein the input signals comprise control information;
generate, based on the control information, a control sequence for transfer of data between the non-volatile logic element array and the plurality of volatile storage elements, wherein the control sequence selects between a sequential, a parallel, and a combination of sequential and parallel transfer of the data between the non-volatile logic element array and the plurality of volatile storage elements;
in response to determining, in accordance with the input signals, to transfer the data to the non-volatile logic element array, transfer the data based on the control sequence from the plurality of volatile storage elements to the non-volatile logic element array and stop the system clock until the transfer is complete; and
in response to determining, in accordance with the input signals, to transfer the data to the plurality of volatile storage elements, transfer the data based on the control sequence from the non-volatile logic element array to the plurality of volatile storage elements.
2. The computing apparatus of claim 1 , wherein the at least one non-volatile logic controller is further configured to receive the input signals through a user interface.
3. The computing apparatus of claim 1 , wherein the at least one non-volatile logic controller is further configured to receive the input signals from a separate computing element.
4. The computing apparatus of claim 3 , wherein the at least one non-volatile logic controller is further configured to receive the input signals from an application executed by the separate computing element.
5. The computing apparatus of claim 4 , wherein the separate computing element is configured to execute the application to determine a reading sequence for the non-volatile logic element array based at least in part on the determination of power and computing resource requirements for the computing apparatus.
6. A method, comprising:
receiving, by at least one non-volatile logic controller, input signals, wherein the input signals comprise control information; and
generating, based on the control information, a control sequence for transfer of data between a non-volatile logic element array and a plurality of volatile storage elements, wherein the control sequence selects between a sequential, a parallel, and a combination of sequential and parallel transfer of the data between the non-volatile logic element array and the plurality of volatile storage elements;
in response to determining, in accordance with the input signals, to transfer the data to the non-volatile logic element array, transferring the data based on the control sequence from the plurality of volatile storage elements to the non-volatile logic element array and stopping a system clock until the transferring is complete;
in response to determining, in accordance with the input signals, to transfer the data to the plurality of volatile storage elements, transfer the data based on the control sequence from the non-volatile logic element array to the plurality of volatile storage elements.
7. The method of claim 6 , further comprising receiving, by the at least one non-volatile logic controller, the input signals through a user interface.
8. The method of claim 6 , further comprising the at least one non-volatile logic controller receiving the input signals from a separate computing element.
9. The method of claim 8 , further comprising the at least one non-volatile logic controller receiving the input signals from an application executed by the separate computing element.
10. The method of claim 9 , further comprising the separate computing element executing the application, to determine a reading sequence for the non-volatile logic element array, based on the determination of power and computing resource requirements for a computing apparatus.
11. An apparatus, comprising:
a system clock;
a circuit, comprising:
a non-volatile logic element array; and
a plurality of volatile storage elements coupled to the non-volatile logic element array, the plurality of volatile storage elements comprising a first volatile storage element, the first volatile storage element comprising:
a primary latch in a first power domain at a first voltage; and
a secondary latch coupled to the primary latch, the secondary latch in a second power domain at a second voltage;
at least one non-volatile logic controller coupled to the non-volatile logic element array, the at least one non-volatile logic controller configured to:
receive input signals, wherein the input signals comprise control information;
generate, based on the control information, a control sequence for transfer of data between the non-volatile logic element array and the plurality of volatile storage elements, wherein the control sequence selects between a sequential, a parallel, and a combination of sequential and parallel transfer of the data between the non-volatile logic element array and the plurality of volatile storage elements;
in response to determining, in accordance with the input signals, to transfer the data to the non-volatile logic element array, stop the system clock based on the control sequence from the plurality of volatile storage elements to the non-volatile logic element array and stop the system clock until the transfer is complete; and
in response to determining, in accordance with the input signals, to transfer the data to the plurality of volatile storage elements, transfer the data based on the control sequence from the non-volatile logic element array to the plurality of volatile storage elements.
12. The apparatus of claim 11 , wherein the circuit further comprises a multiplexer coupled between the non-volatile logic element array and the plurality of volatile storage elements.
13. The apparatus of claim 11 , wherein the non-volatile logic element array is an array of ferroelectric capacitor based bitcells.
14. The apparatus of claim 11 , wherein the non-volatile logic element array is in a third power domain at a third voltage.
15. The apparatus of claim 14 , wherein the first voltage is lower than the third voltage.
16. The apparatus of claim 11 , wherein the plurality of volatile storage elements is a plurality of retention flip flops.
17. The computing apparatus of claim 1 , wherein the non-volatile logic element array is configured to store a boot state representing a state of the computing apparatus after a given amount of a boot process is complete.
18. The computing apparatus of claim 1 , wherein the circuit further comprises a multiplexer coupled between the non-volatile logic element array and the plurality of volatile storage elements.
19. The computing apparatus of claim 1 , the plurality of volatile storage elements comprising a first volatile storage element, the first volatile storage element comprising:
a primary latch in a first power domain at a first voltage; and
a secondary latch coupled to the primary latch, the secondary latch in a second power domain at a second voltage, wherein the second power domain is configured to be powered up or down independently of the first power domain, and wherein the non-volatile logic element array is in a third power domain at a third voltage, wherein the third power domain is configured to be powered up or down independently of the first power domain and the second power domain.
20. The apparatus of claim 11 , wherein the circuit is at a first location, the apparatus further comprising a second circuit at a second location, wherein the second location is different from the first location, the second circuit comprising:
a second non-volatile logic element array; and
a second plurality of volatile storage elements coupled to the second non-volatile logic element array and to the at least one non-volatile logic controller.