Control of NAND flash memory for al applications
A system comprises: a three-dimensional flash memory comprising a plurality of cells; and a controller coupled to the three-dimensional flash memory, configured to: select a block of cells in the three-dimensional flash memory; perform a matrix multiplication on the matrix stored in the block of cells, including performing a vector multiplication in a single sensing step; and output a matrix multiplication result. A matrix is stored in the block of cells.
1. A system, comprising:
a three-dimensional flash memory comprising a plurality of cells; and
a controller coupled to the three-dimensional flash memory, configured to:
select a block of cells in the three-dimensional flash memory, wherein:
a matrix is stored in the block of cells; and
the block of cells is selected by using one or more select gate drains (SGDs) and one or more word lines;
perform a matrix multiplication on the matrix stored in the block of cells, including performing a vector multiplication in a single sensing step; and
output a matrix multiplication result.
2. The system of claim 1 , wherein the block of cells is a subset of cells in the three-dimensional flash memory.
3. The system of claim 2 , wherein the three-dimensional flash memory includes a NAND flash memory.
4. The system of claim 2 , wherein the selected block of cells forms a cuboid.
5. The system of claim 1 , wherein:
the block of cells is a first block of cells;
the matrix is a first matrix;
the matrix multiplication is a first matrix multiplication; and
the controller is further configured to:
select a second block of cells storing a second matrix; and
perform a second matrix multiplication on the second matrix substantially in parallel with the first matrix multiplication.
6. The system of claim 1 , wherein:
the matrix is a weight matrix; and
the matrix multiplication includes multiplying an activation matrix with the weight matrix.
7. The system of claim 1 , wherein:
the matrix is a weight matrix;
the matrix multiplication includes multiplying an activation matrix with the weight matrix; and
to input the activation matrix includes to configure the one or more word lines.
8. The system of claim 1 , wherein the matrix multiplication includes multiplying a scalar with the matrix.
9. The system of claim 1 , wherein:
the matrix multiplication includes multiplying a scalar with the matrix; and
the scalar is configured by configuring a source plate voltage.
10. The system of claim 1 , further including an integrated processor.
11. A method, comprising:
selecting a block of cells in a three-dimensional flash memory, wherein:
a matrix is stored in the block of cells; and
the block of cells is selected by using one or more select gate drains (SGDs) and one or more word lines;
performing a matrix multiplication on the matrix stored in the block of cells, including performing a vector multiplication in a single sensing step; and
outputting a matrix multiplication result.
12. The method of claim 11 , wherein the block of cells is a subset of cells in the three-dimensional flash memory.
13. The method of claim 12 , wherein the three-dimensional flash memory includes a NAND flash memory.
14. The method of claim 12 , wherein the selected block of cells forms a cuboid.
15. The method of claim 11 , wherein:
the block of cells is a first block of cells;
the matrix is a first matrix;
the matrix multiplication is a first matrix multiplication; and
the method further comprising:
selecting a second block of cells storing a second matrix; and
performing a second matrix multiplication on the second matrix substantially in parallel with the first matrix multiplication.
16. The method of claim 11 , wherein:
the matrix is a weight matrix; and
the matrix multiplication includes multiplying an activation matrix with the weight matrix.
17. The method of claim 11 , wherein:
the matrix is a weight matrix;
the matrix multiplication includes multiplying an activation matrix with the weight matrix; and
inputting the activation matrix includes to configure the one or more word lines.
18. The method of claim 11 , wherein the matrix multiplication includes multiplying a scalar with the matrix.
19. The method of claim 11 , wherein:
the matrix multiplication includes multiplying a scalar with the matrix; and
the scalar is configured by configuring a source plate voltage.
20. A computer program product for acceleration of matrix operations, the computer program product being embodied in a tangible computer readable storage medium and comprising computer instructions for:
selecting a block of cells in a three-dimensional flash memory, wherein:
a matrix is stored in the block of cells; and
the block of cells is selected by using one or more select gate drains (SGDs) and one or more word lines;
performing a matrix multiplication on the matrix stored in the block of cells, including performing a vector multiplication in a single sensing step; and
outputting a matrix multiplication result.