Core-to-core cache stashing and target discovery

1. A method of data transfer comprising:

writing, by a first processor core of a data processing system, data associated with a first data address to a first cache;

executing, by the first processor core, a stash instruction having, as a first operand, a virtual address corresponding to the first data address;

determining a second processor core of the data processing system to be a stash target for a stash message, including:

when the stash instruction includes a second operand, determining the stash target based on the second operand, and

when the stash instruction does not include the second operand, accessing a first entry associated with the first data address in a Stash Target Table, and

determining the stash target based on the first entry;

sending the stash message to the second processor core, the stash message including the first data address; and

responsive to receiving the stash message, the second processor core storing the data associated with the first data address in a cache of the second processor core.

2. The method of claim 1 , further comprising the first processor core determining the second processor core to be the stash target and sending the stash message to the second processor core.

3. The method of claim 1 , where the second operand of the stash instruction includes an identifier of the second processor core.

4. The method of claim 1 , where the stash message includes the data associated with the first data address.

5. The method of claim 1 , where the first cache is a cache of the first processor core and the second processor core storing the data associated with the first data address in the cache of the second processor core includes:

the second processor core requesting the data associated with the first data address; and

the first processor core forwarding the data associated with the first data address to the second processor core.

6. The method of claim 1 , further comprising, prior to said determining:

sending, by the second processor core, a target registration message for the first data address; and

generating the first entry in the Stash Target Table, the first entry identifying the second processor core as a target for data associated with the first data address.

7. The method of claim 1 , further comprising, prior to said determining:

generating the first entry in the Stash Target Table for a first data address responsive to receiving a prior stash request for the first data address from the first processor core.

8. The method of claim 1 , further comprising,

updating the first entry in the Stash Target Table responsive to a change in a coherency state of the data associated with the first data address from unique to shared or shared to unique in a cache of the first processor core.

9. The method of claim 1 , further comprising, prior to said writing:

invalidating data associated with the first data address stored in caches of one or more third processor cores responsive to a request by the first processor core for ownership of the data associated with the first data address; and

updating the first entry in the stash target Table to identify the one or more third processor cores as stash targets for the first data address.

10. The method of claim 1 , further comprising:

sending, by the first processor core, a first stash request to a home agent of the data processing system, the first stash request including the first data address and the home agent configured for said determining the second processor core of the data processing system to be the stash target for the stash message and said sending the stash message to the second processor core.

11. The method of claim 10 , where said determining includes accessing a first entry in a Stash Target Table, the first entry associated with the first data address.

12. The method of claim 11 , further comprising, prior to said determining:

generating, by the home agent, the first entry in the Stash Target Table for a first data address responsive to receiving a prior stash request for the first data address from the first processor core.

13. The method of claim 12 , further comprising, prior to said determining:

forwarding, by the home agent, a read request for the data associated with the first data address from the second processor core to the first processor core;

updating or creating, by the home agent, the first entry in the Stash Target Table to identify the second processor core as a stash target for the first data address; and

forwarding, by the first processor core, the data associated with the first data address to the second processor core for storing in the cache of the second processor core.

14. The method of claim 12 , further comprising:

updating the first entry in the Stash Target Table responsive to a change in a coherency state of the data associated with the first data address from unique to shared or shared to unique in a cache of the first processor core.

15. The method of claim 10 , where the second processor core storing the data associated with the first data address in the cache of the second processor core comprises:

sending, by the second processor core, a request to the home agent;

the home agent sending a message to the first processor core; and

the first processor core forwarding the data associated with the first data address to the second processor core.

16. A method of data transfer comprising:

monitoring transactions from a plurality of processor cores of a data processing system that allocate and deallocate data into caches of the plurality of processor cores;

predicting, based at least in part on the monitored transactions, one or more processor cores of the plurality of processor cores to be stash target cores for data associated with a first data address;

executing, by a first processor core of the plurality of processor cores, a first stash instruction for the first data address;

sending a stash message to the stash target cores, the stash message notifying the stash target cores of the data associated with the first data address and produced by the first processor core; and

responsive to receiving the stash message, a second processor core of the one or more stash target cores storing the data associated with the first data address in a cache of the second processor core.

17. The method of claim 16 , further comprising, prior to executing the first stash instruction:

executing, by the first processor core, a second stash instruction for the first data address;

storing, responsive to executing the second stash instruction, an entry in a Stash Target Table for the first data address; and,

updating the entry in the Stash Target Table to identify the second processor core as a stash target core, responsive to the second processor core becoming, or ceasing to become, a sharer of the data associated with the first data address,

where said predicting one or more processor cores of the plurality of processor cores to be stash target cores for data associated with the first data address includes accessing the entry in the Stash Target Table for the first data address.

18. The method of claim 16 , further comprising, prior to executing the first stash instruction:

executing a register instruction by the second processor core for the first data address; and

creating or updating an entry in a Stash Target Table responsive to the register instruction, the entry identifying the second processor core as a stash target core for the first data address,

where said predicting one or more processor cores of the plurality of processor cores to be stash target cores for data associated with the first data address includes accessing the entry in the Stash Target Table for the first data address.

19. A data processing system comprising:

an interconnect fabric;

a plurality of processor cores interconnected by the interconnect fabric, a first processor core of the plurality of processor cores configured for writing data associated with a first data address to a cache and executing a first stash instruction for the first data address;

Stash Target Table control circuitry configured to:

monitor transactions from a plurality of processor cores of a data processing system that allocate and deallocate data into caches of the plurality of processor cores;

create and update entries in a Stash Target Table;

predict, responsive to the first stash instruction, one or more processor cores of the plurality of processor cores to be stash target cores for the data associated with the first data address;

send a stash message to the stash target cores, the stash message configured to notify the stash target cores of the data associated with the first data address and produced by the first processor core; and

where a second processor core of the one or more stash target cores is configured to store the data associated with the first data address in a cache of the second processor core responsive to receiving the stash message.

20. The data processing system of claim 19 , further comprising:

a home agent, coupled to the plurality of processor cores by the interconnect fabric,

the home agent configured to provide a point of coherences and serialization for the data processing system,

where the home agent includes the Stash Target Table control circuitry.

21. The data processing system of claim 19 , where the first processor core includes the Stash Target Table control circuitry.

22. The data processing system of claim 19 , where the Stash Target Table control circuitry is further configured to:

create an entry in the Stash Target Table responsive to a stash instruction from the first processor core or a register request from the second processor core;

insert the second processor core as a stash target into the entry responsive to a read request or a stash register request sent from the second processor core; and

insert sharers of the data, other than the first processor core, as stash targets into the entry responsive to a stash instruction from the first processor core or a change of coherency state of the data associated with a first data address from shared to owned by the first processor core.