IP Library Granted Patent US 11,264,466
Granted Patent B2
US 11,264,466 · App. 16/801,993 · Granted Mar 1, 2022

Schottky barrier diode

Inventors: Masaru Takizawa (Tokyo, JP); Akito Kuramata (Tokyo, JP)
Assignee: TAMURA CORPORATION
H01L29/24H01L21/02414H01L21/02433H01L21/02565H01L21/02576H01L21/02631H01L29/0619H01L29/0661H01L29/267H01L29/66969H01L29/872H01L29/47
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Quick Facts
Patent No.
US 11,264,466
App. No.
16/801,993
Granted
Mar 1, 2022
Kind
B2
Abstract

A semiconductor device includes a semiconductor layer including a Ga 2 O 3 -based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga 2 O 3 -based single crystal.

Claims (26)

1. A semiconductor device, comprising;

a first semiconductor layer including Ga 2 O 3 -based single crystal and having an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga 2 O 3 -based single crystal; and

a second semiconductor layer including an n-type Ga 2 O 3 -based single crystal on a bottom side of the first semiconductor layer and having an electron carrier concentration which is greater than the electron carrier concentration in the first semiconductor layer; and an electrode layer that is in Schottky-contact with the first semiconductor layer, wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 18 /cm 3 ,

wherein the first semiconductor layer includes:

a flat upper surface formed on an opposite side to the second semiconductor layer;

a side surface inclined so as to extend from an outer edge of the upper surface toward the second semiconductor layer; and

a lower surface parallel to the upper surface and is formed on an outer side of the side surface so as to surround the side surface,

wherein the electrode layer is formed on the upper surface of the first semiconductor layer at a predetermined distance from the side surface of the first semiconductor layer, and wherein the semiconductor device further comprises a passivation film formed in a region between a periphery of the electrode layer to a portion of the lower surface of the first semiconductor layer on the side surface of first semiconductor layer.

2. The semiconductor device according to claim 1 , further comprising a resistive or p-type layer formed in a portion of the first semiconductor layer.

3. A semiconductor device, comprising;

a first semiconductor layer including Ga 2 O 3 -based single crystal and having an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga 2 O 3 -based single crystal;

a second semiconductor layer including an n-type Ga 2 O 3 -based single crystal on a bottom side of the first semiconductor layer and having an electron carrier concentration which is greater than the electron carrier concentration in the first semiconductor layer; and

an electrode layer that is in Schottky-contact with the first semiconductor layer, wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 18 /cm 3 ,

wherein a passivation film is formed on an upper surface of the first semiconductor layer at a periphery thereof,

wherein the electrode layer is formed at a middle portion of the upper surface of the first semiconductor layer,

wherein a portion of the electrode layer in a peripheral region covers the passivation film, and

wherein the semiconductor device further comprises a resistive or p-type layer formed in the first semiconductor layer on an upper surface side in a region including an interface between the electrode layer and the passivation film.

4. The semiconductor device according to claim 1 , wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 17 /cm 3 .

5. The semiconductor device according to claim 1 , wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 16 /cm 3 .

6. The semiconductor device according to claim 1 , wherein the electron carrier concentration in the second semiconductor layer is greater than 1×10 18 /cm 3 .

7. The semiconductor device according to claim 2 , wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 17 /cm 3 .

8. The semiconductor device according to claim 2 , wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 16 /cm 3 .

9. The semiconductor device according to claim 2 , wherein the electron carrier concentration in the second semiconductor layer is greater than 1×10 18 /cm 3 .

10. The semiconductor device according to claim 3 , wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 17 /cm 3 .

11. The semiconductor device according to claim 3 , wherein the electron carrier concentration in the first semiconductor layer is less than 1×10 16 /cm 3 .

12. The semiconductor device according to claim 3 , wherein the electron carrier concentration in the second semiconductor layer is greater than 1×10 18 /cm 3 .

Priority Claims (1)
JP 2011-245519 · Nov 9, 2011 · national
Continuity (5)
Continuation 15436508 · Feb 17, 2017
Continuation 15208469 · Jul 12, 2016
Continuation 14918129 · Oct 20, 2015
Continuation 14357176
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