Translation lookaside buffer invalidation for merged invalidation requests across power boundaries

1. A method of memory management, comprising:

receiving a first request to clear one or more entries of a translation lookaside buffer (TLB);

receiving a second request to clear one or more entries of the TLB;

bundling the first request with the second request;

determining that a processor associated with the TLB transitioned to an inactive mode; and

dropping the bundled first and second requests based on the determination.

2. The method of claim 1 , further comprising:

determining a first timestamp based on a first time associated with receiving the first request;

determining a second timestamp based on a second time associated with receiving the second request;

associating the first timestamp with the first request;

associating the second timestamp with the second request; and

wherein the determining is based on the first and second timestamps.

3. The method of claim 2 , further comprising:

determining a timeline based on a first indication that the processor transitioned to an active mode and a second indication that the processor transitioned to the inactive mode, and

wherein the determining is based on a comparison of the first and second timestamps with the timeline.

4. The method of claim 3 , further comprising:

receiving a third request to clear one or more entries of the TLB;

bundling the third request with the first and second requests;

determining that the third request was received when the processor was in the active mode based on a comparison of a timestamp associated with the third request and the timeline; and

transmitting a TLB invalidation (TLBI) request based on the third request to the TLB.

5. The method of claim 1 , wherein the processor transitioned to the inactive mode after receiving at least the first request.

6. The method of claim 1 , wherein the processor comprises one of a graphics processing unit or a central processing unit.

7. The method of claim 1 , wherein transitioning to the inactive mode comprises clearing the TLB.

8. A non-transitory program storage device comprising instructions stored thereon to cause one or more processors to:

receive a first request to clear one or more entries of a translation lookaside buffer (TLB);

receive a second request to clear one or more entries of the TLB;

bundle the first request with the second request;

determine that a processor associated with the TLB transitioned to an inactive mode; and

drop the bundled first and second requests based on the determination.

9. The non-transitory program storage device of claim 8 , wherein the instructions further cause the one or more processors to:

determine a first timestamp based on a first time associated with receiving the first request;

determine a second timestamp based on a second time associated with receiving the second request;

associate the first timestamp with the first request;

associate the second timestamp with the second request; and

wherein the determining is based on the first and second timestamps.

10. The non-transitory program storage device of claim 9 , wherein the instructions further cause the one or more processors to:

determine a timeline based on a first indication that the processor transitioned to an active mode and a second indication that the processor transitioned to the inactive mode, and

wherein the determining is based on a comparison of the first and second timestamps with the timeline.

11. The non-transitory program storage device of claim 10 , wherein the instructions further cause the one or more processors to:

receive a third request to clear one or more entries of the TLB;

bundle the third request with the first and second requests;

determine that the third request was received when the processor was in the active mode based on a comparison of a timestamp associated with the third request and the timeline; and

transmit a TLB invalidation (TLBI) request based on the third request to the TLB.

12. The non-transitory program storage device of claim 8 , wherein the processor transitioned to the inactive mode after receiving at least the first request.

13. The non-transitory program storage device of claim 8 , wherein the processor comprises one of a graphics processing unit or a central processing unit.

14. The non-transitory program storage device of claim 8 , wherein transitioning to the inactive mode comprises clearing the TLB.

15. An electronic device, comprising:

a memory; and

one or more processors operatively coupled to the memory, wherein the one or more processors are configured to execute instructions causing the one or more processors to:

receive a first request to clear one or more entries of a translation lookaside buffer (TLB);

receive a second request to clear one or more entries of the TLB;

bundle the first request with the second request;

determine that a processor of the one or more processors associated with the TLB transitioned to an inactive mode; and

drop the bundled first and second requests based on the determination.

16. The device of claim 15 , wherein the instructions further cause the one or more processors to:

determine a first timestamp based on a first time associated with receiving the first request;

determine a second timestamp based on a second time associated with receiving the second request;

associate the first timestamp with the first request;

associate the second timestamp with the second request; and

wherein the determining is based on the first and second timestamps.

17. The device of claim 16 , wherein the instructions further cause the one or more processors to:

determine a timeline based on a first indication that the processor transitioned to an active mode and a second indication that the processor transitioned to the inactive mode, and

wherein the determining is based on a comparison of the first and second timestamps with the timeline.

18. The device of claim 17 , wherein the instructions further cause the one or more processors to:

receive a third request to clear one or more entries of the TLB;

bundle the third request with the first and second requests;

determine that the third request was received when the processor was in the active mode based on a comparison of a timestamp associated with the third request and the timeline; and

transmit a TLB invalidation (TLBI) request based on the third request to the TLB.

19. The device of claim 15 , wherein the processor transitioned to the inactive mode after receiving at least the first request.

20. The device of claim 15 , wherein the processor comprises one of a graphics processing unit or a central processing unit.