Memory device
A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.
1. A memory device, comprising:
a memory structure comprising:
a resistive switching layer, shaped as a cup and having an inner surface to define an opening;
a conductive pillar, disposed in the opening; and
a barrier layer, disposed between the resistive switching layer and the conductive pillar;
a word line, electrically connected to the conductive pillar;
a plurality of resistive layers respectively distributed on the outer surface of the resistive switching layer, wherein a portion of the memory structure connected to one of the plurality of resistive layers constitutes a memory cell; and
a plurality of bit lines, electrically connected to the plurality of resistive layers, respectively, wherein each resistive layer has a first sidewall and a second sidewall opposite to each other, the first sidewall is in direct contact with the resistive switching layer, and the second sidewall is in direct contact with a corresponding bit line.
2. The memory device according to claim 1 , wherein a resistance value of the plurality of resistive layers is 1 KOhm to 3 KOhm.
3. The memory device according to claim 1 , wherein a resistance value of the plurality of resistive layers is greater than a resistance value of the conductive pillar, a resistance value of the word line, and a resistance value of the plurality of bit lines.
4. The memory device according to claim 1 , wherein a ratio of a resistance value of the resistive switching layer to a resistance value of the plurality of resistive layers is 2 to 100.
5. The memory device according to claim 1 , wherein a length of the plurality of resistive layers is 10 nanometers to 100 nanometers.
6. The memory device according to claim 1 , wherein a material of the plurality of resistive layers comprises TaN, TiN, or a combination thereof.
7. The memory device according to claim 1 , wherein the barrier layer is conformally disposed in the opening to have a cup-shaped structure, and a material of the barrier layer comprises Al 2 O 3 , TiO x , or a combination thereof.
8. The memory device according to claim 1 , wherein a material of the conductive pillar comprises Ti, Ta, Al, W, or a combination thereof.
9. The memory device according to claim 1 , wherein a material of the resistive switching layer comprises HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , or a combination thereof.
10. A memory device, comprising:
a memory structure comprising:
a resistive switching layer, shaped as a cup and having an inner surface to define an opening;
a conductive pillar, disposed in the opening; and
a barrier layer, disposed between the resistive switching layer and the conductive pillar;
a select transistor, electrically connected to the conductive pillar;
a plurality of resistive layers respectively distributed on the outer surface of the resistive switching layer, wherein a portion of the memory structure connected to one of the plurality of resistive layers constitutes a memory cell; and
a plurality of bit lines comprising a plurality of odd bit lines and a plurality of even bit lines, wherein the plurality of odd bit lines are electrically connected to each other and connected to corresponding resistive layers at a first side of the conductive pillar, and the plurality of even bit lines are electrically connected to each other and connected to other corresponding resistive layers at a second side opposite to the first side of the conductive pillar, wherein each resistive layer has a first sidewall and a second sidewall opposite to each other, the first sidewall is in direct contact with the resistive switching layer, and the second sidewall is in direct contact with a corresponding bit line.