Bipolar junction device
The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.
1. A bipolar junction transistor (BJT), comprising:
a first epitaxial feature disposed over a well region;
a second epitaxial feature disposed over the well region;
a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature;
a gate structure wrapping around each of the vertical stack of channel members;
a first electrode coupled to the well region;
an emitter electrode disposed over and coupled to the first epitaxial feature; and
a second electrode disposed over and coupled to the second epitaxial feature.
2. The BJT of claim 1 , wherein the gate structure is electrically floating.
3. The BJT of claim 1 ,
wherein the first epitaxial feature and the second epitaxial feature comprise a first dopant,
wherein the well region comprises a second dopant different from the first dopant,
wherein the first electrode comprises a base electrode, and
wherein the second electrode comprises a collector electrode.
4. The BJT of claim 1 , further comprising a silicide layer disposed between the well region and the first electrode.
5. The BJT of claim 4 , further comprising an epitaxial layer disposed between the silicide layer and the well region.
6. The BJT of claim 1 , further comprising an isolation structure disposed below the first epitaxial feature, wherein the isolation structure prevents the first electrode from extending directly below the first epitaxial feature.
7. The BJT of claim 1 , further comprising a plurality of inner spacer features interleaving the vertical stack of channel members.
8. A semiconductor structure, comprising:
a first epitaxial feature and a second epitaxial feature disposed over a well region of a semiconductor body;
a silicide layer disposed below and in contact with the semiconductor body;
a vertical stack of nanostructures each extending lengthwise between the first epitaxial feature and the second epitaxial feature; and
a gate structure wrapping around each of the vertical stack of nanostructures,
wherein the gate structure is electrically floating.
9. The semiconductor structure of claim 8 , further comprising:
a first electrode coupled to the well region;
an emitter electrode disposed over and coupled to the first epitaxial feature; and
a second electrode disposed over and coupled to the second epitaxial feature.
10. The semiconductor structure of claim 9 , further comprising an epitaxial layer disposed between the silicide layer and the well region.
11. The semiconductor structure of claim 8 , wherein each of the first epitaxial feature and the second epitaxial feature is spaced apart from the gate structure by a plurality of inner spacer features.
12. The semiconductor structure of claim 11 , wherein the plurality of inner spacer features comprise silicon oxide, hafnium silicide, silicon oxycarbide, silicon oxynitride, aluminum oxide, zirconium silicide, aluminum oxynitride, zirconium oxide, hafnium oxide, titanium oxide, zirconium aluminum oxide, zinc oxide, tantalum oxide, lanthanum oxide, yittrium oxide, tantalum carbonitride, silicon nitride, silicon oxycarbonitride, silicon, zirconium nitride, or silicon carbonitride.
13. The semiconductor structure of claim 8 , wherein the silicide layer and the semiconductor body comprise a Schottky junction.
14. The semiconductor structure of claim 8 ,
wherein the well region comprises a thickness measured from the silicide layer,
wherein the thickness is between about 50 nm and about 100 nm.
15. A semiconductor structure, comprising:
a first epitaxial feature and a second epitaxial feature disposed over a well region of a semiconductor body;
a plurality of nanostructures each extending lengthwise between the first epitaxial feature and the second epitaxial feature;
a gate structure wrapping around each of the plurality of nanostructures;
a first electrode coupled to the well region;
an emitter electrode disposed over and coupled to the first epitaxial feature; and
a second electrode disposed over and coupled to the second epitaxial feature,
wherein the gate structure is electrically floating.
16. The semiconductor structure of claim 15 ,
wherein the first epitaxial feature and the second epitaxial feature comprise a first dopant,
wherein the well region comprises a second dopant different from the first dopant,
wherein the first electrode comprises a base electrode, and
wherein the second electrode comprises a collector electrode.
17. The semiconductor structure of claim 15 , further comprising a silicide layer disposed between the well region and the first electrode.
18. The semiconductor structure of claim 17 , further comprising an epitaxial layer disposed between the silicide layer and the well region.
19. The semiconductor structure of claim 18 , wherein the epitaxial layer comprises silicon and an n-type dopant.
20. The semiconductor structure of claim 15 , further comprising an isolation structure disposed below the first epitaxial feature, wherein the isolation structure prevents the first electrode from extending directly below the first epitaxial feature.