Pixel circuit and method for improving image quality at low driving frequency
A pixel circuit includes a light-emitting element, a first transistor, a second transistor operating based on a first gate signal, a third transistor operating based on a second gate signal, a fourth transistor operating based on an initialization control signal, a fifth transistor operating based on an emission control signal, a sixth transistor operating based on the emission control signal, a seventh transistor, of which one terminal is connected to the light-emitting element, operating based on a bias control signal, an eighth transistor, of which one terminal is connected to the driving transistor, operating based on the bias control signal, a storage capacitor, and the light-emitting element. The pixel circuit performs a display-scan operation in a first case where a driving time of a panel driving frame is a minimum driving time and performs a display-scan operation and at least one self-scan operation in a second case where the driving time is different from the minimum driving time.
1. A pixel circuit comprising:
a first transistor including a first terminal connected to a first node, a gate terminal connected to a second node, and a second terminal connected to a third node;
a second transistor including a first terminal connected to a data line, a second terminal connected to the first node, and a gate terminal that receives a first gate signal;
a third transistor including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal that receives a second gate signal;
a fourth transistor including a first terminal connected to the second node, a second terminal that receives a first initialization voltage, and a gate terminal that receives an initialization control signal;
a fifth transistor including a first terminal that receives a first power voltage, a second terminal connected to the first node, and a gate terminal that receives an emission control signal;
a sixth transistor including a first terminal connected to the third node, a second terminal connected to a fourth node, and a gate terminal that receives the emission control signal;
a seventh transistor including a first terminal connected to the fourth node, a second terminal that receives a second initialization voltage, and a gate terminal that receives a bias control signal;
an eighth transistor including a first terminal connected to the third node, a second terminal that receives a bias voltage, and a gate terminal that receives the bias control signal;
a storage capacitor including a first terminal that receives the first power voltage and a second terminal connected to the second node; and
a light emitting element including a first terminal connected to the fourth node and a second terminal that receives a second power voltage lower than the first power voltage,
wherein the pixel circuit performs a display-scan operation in a first case where a driving time of a panel driving frame is a minimum driving time, and the pixel circuit performs a display-scan operation and at least one self-scan operation in a second case where the driving time of the panel driving frame is different from the minimum driving time.
2. The pixel circuit of claim 1 , wherein, when the pixel circuit performs the display-scan operation, each of the first gate signal, the second gate signal, the initialization control signal, the bias control signal, and the emission control signal includes at least one turn-on voltage period.
3. The pixel circuit of claim 2 , wherein the at least one turn-on voltage period of the initialization control signal, the at least one turn-on voltage period of the first gate signal, the at least one turn-on voltage period of the second gate signal, and the at least one turn-on voltage period of the bias control signal are positioned in a turn-off voltage period of the emission control signal.
4. The pixel circuit of claim 3 , wherein the at least one turn-on voltage period of the bias control signal is positioned after the at least one turn-on voltage period of the second gate signal.
5. The pixel circuit of claim 3 , wherein the at least one turn-on voltage period of the bias control signal includes a first turn-on voltage period positioned before the at least one turn-on voltage period of the initialization control signal and a second turn-on voltage period positioned after the at least one turn-on voltage period of the second gate signal.
6. The pixel circuit of claim 1 , wherein, when the pixel circuit performs the self-scan operation, each of the bias control signal and the emission control signal includes at least one turn-on voltage period, and each of the first gate signal, the second gate signal, and the initialization control signal is turned off.
7. The pixel circuit of claim 6 , wherein the at least one turn-on voltage period of the bias control signal is positioned in a turn-off voltage period of the emission control signal.
8. The pixel circuit of claim 6 , wherein the at least one turn-on voltage period of the bias control signal includes a first turn-on voltage period and a second turn-on voltage period that are temporally spaced apart from each other in a turn-off voltage period of the emission control signal.
9. The pixel circuit of claim 1 , wherein the bias voltage and the second initialization voltage are changed based on the driving time of the panel driving frame.
10. The pixel circuit of claim 1 , further comprising:
a boost capacitor including a first terminal connected to the second node and a second terminal connected to the gate terminal of the third transistor.
11. A pixel circuit comprising:
a first transistor including a first terminal connected to a first node, a gate terminal connected to a second node, and a second terminal connected to a third node;
a second transistor including a first terminal connected to a data line, a second terminal connected to the first node, and a gate terminal that receives a first gate signal;
a third transistor including a first terminal connected to the third node, a second terminal connected to the second node, and a gate terminal that receives a second gate signal;
a fourth transistor including a first terminal connected to the second node, a second terminal that receives a first initialization voltage, and a gate terminal that receives an initialization control signal;
a fifth transistor including a first terminal that receives a first power voltage, a second terminal connected to the first node, and a gate terminal that receives an emission control signal;
a sixth transistor including a first terminal connected to the third node, a second terminal connected to a fourth node, and a gate terminal that receives the emission control signal;
a seventh transistor including a first terminal connected to the fourth node, a second terminal that receives a second initialization voltage, and a gate terminal that receives a bias control signal;
an eighth transistor including a first terminal connected to the first node, a second terminal that receives a bias voltage, and a gate terminal that receives the bias control signal;
a storage capacitor including a first terminal that receives the first power voltage and a second terminal connected to the second node; and
a light emitting element including a first terminal connected to the fourth node and a second terminal that receives a second power voltage lower than the first power voltage,
wherein the pixel circuit performs a display-scan operation in a first case where a driving time of a panel driving frame is a minimum driving time, and the pixel circuit performs a display-scan operation and at least one self-scan operation in a second case where the driving time of the panel driving frame is different from the minimum driving time.
12. The pixel circuit of claim 11 , wherein, when the pixel circuit performs the display-scan operation, each of the first gate signal, the second gate signal, the initialization control signal, the bias control signal, and the emission control signal includes at least one turn-on voltage period.
13. The pixel circuit of claim 12 , wherein the at least one turn-on voltage period of the initialization control signal, the at least one turn-on voltage period of the first gate signal, the at least one turn-on voltage period of the second gate signal, and the at least one turn-on voltage period of the bias control signal are positioned in a turn-off voltage period of the emission control signal.
14. The pixel circuit of claim 13 , wherein the at least one turn-on voltage period of the bias control signal is positioned after the at least one turn-on voltage period of the second gate signal.
15. The pixel circuit of claim 13 , wherein the at least one turn-on voltage period of the bias control signal includes a first turn-on voltage period positioned before the at least one turn-on voltage period of the initialization control signal and a second turn-on voltage period positioned after the at least one turn-on voltage period of the second gate signal.
16. The pixel circuit of claim 11 , wherein, when the pixel circuit performs the self-scan operation, each of the bias control signal and the emission control signal includes at least one turn-on voltage period, and each of the first gate signal, the second gate signal, and the initialization control signal is turned off.
17. The pixel circuit of claim 16 , wherein the at least one turn-on voltage period of the bias control signal is positioned in a turn-off voltage period of the emission control signal.
18. The pixel circuit of claim 16 , wherein the at least one turn-on voltage period of the bias control signal includes a first turn-on voltage period and a second turn-on voltage period that are temporally spaced apart from each other in a turn-off voltage period of the emission control signal.
19. The pixel circuit of claim 11 , wherein the bias voltage and the second initialization voltage are changed based on the driving time of the panel driving frame.
20. The pixel circuit of claim 11 , further comprising:
a boost capacitor including a first terminal connected to the second node and a second terminal connected to the gate terminal of the third transistor.