Semiconductor device and method of fabricating the same
A semiconductor device comprises a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a front-side metallization, a backside metallization, and conductive contacts. The first gate structure and the second gate structure disposed respectively in the front-side and back side of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structures. The front-side metallization is disposed on the front-side of the buried dielectric layer, and the backside metallization is disposed on the backside of the buried dielectric layer. The conductive contacts penetrate the buried dielectric layer and electrically couple the front-side metallization to the backside metallization.
1. A semiconductor device, comprising:
a buried dielectric layer;
a first gate structure, disposed on a front-side of the buried dielectric layer;
a second gate structure, disposed on a backside of the buried dielectric layer;
a first source/drain region and a second source/drain region, disposed between the first gate structure and the second gate structure;
a front-side metallization, disposed on the front-side of the buried dielectric layer;
a backside metallization, disposed on the backside of the buried dielectric layer; and
a plurality of conductive contacts, penetrating the buried dielectric layer and electrically coupling the front-side metallization to the backside metallization.
2. The semiconductor device of claim 1 , wherein the front-side metallization comprises conductive interconnection and conductive via.
3. The semiconductor device of claim 1 , wherein the backside metallization comprises conductive interconnection and conductive via.
4. The semiconductor device of claim 1 , wherein the front-side metallization comprises a first contact structure disposed on the front-side of the buried dielectric layer and electrically coupled to the first source/drain region.
5. The semiconductor device of claim 1 , wherein a portion of the front-side metallization is electrically coupled to the first gate structure.
6. The semiconductor device of claim 1 , further comprising a first gate contact structure disposed on the front-side of the buried dielectric layer and electrically coupled to the first gate structure.
7. The semiconductor device of claim 1 , wherein the backside metallization comprises a second contact structure disposed on the backside of the buried dielectric layer and electrically coupled to the second source/drain region.
8. The semiconductor device of claim 1 , wherein the first source/drain region and the second source/drain region are disposed on the front-side of the buried dielectric layer.
9. The semiconductor device of claim 1 , further comprising a second gate contact structure disposed on the backside of the buried dielectric layer and electrically coupled to the second gate structure.
10. The semiconductor device of claim 1 , further comprising an interlayer dielectric, disposed on the backside of the buried dielectric layer and covering the second gate structure.
11. The semiconductor device of claim 1 , wherein the backside metallization comprises:
a plurality of conductive patterned features, disposed along the surface of the interlayer dielectric, wherein the conductive patterned features are electrically coupled to the second gate structure, the first source/drain region and the second source/drain region respectively.
12. The semiconductor device of claim 11 , wherein the conductive patterned features are separated from one another.
13. A method of fabricating a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises:
a buried dielectric layer;
a first gate structure, disposed on a front-side of the buried dielectric layer;
a first source/drain region and a second source/drain region, disposed between the buried dielectric layer and the first gate structure; and
a front-side metallization, disposed on the front-side of the buried dielectric layer;
forming a plurality of conductive contacts, penetrating the buried dielectric layer and electrically coupled to the front-side metallization; and
forming a backside metallization on the backside of the buried dielectric layer and electrically coupled to the plurality of conductive contacts.
14. The method of fabricating the semiconductor device of claim 13 , wherein the front-side metallization comprises conductive interconnection and conductive via.
15. The method of fabricating the semiconductor device of claim 13 , wherein the backside metallization comprises conductive interconnection and conductive via.
16. The method of fabricating the semiconductor device of claim 13 , wherein the front-side metallization comprises a first contact structure disposed on the front-side of the buried dielectric layer and electrically coupled to the first source/drain region.
17. The method of fabricating the semiconductor device of claim 13 , wherein a portion of the front-side metallization is electrically coupled to the first gate structure.
18. The method of fabricating the semiconductor device of claim 13 , further comprising a first gate contact structure disposed on the front-side of the buried dielectric layer and electrically coupled to the first gate structure.
19. The method of fabricating the semiconductor device of claim 13 , wherein the backside metallization comprises a second contact structure disposed on the backside of the buried dielectric layer and electrically coupled to the second source/drain region.
20. The method of fabricating the semiconductor device of claim 13 , wherein the first source/drain region and the second source/drain region are disposed on the front-side of the buried dielectric layer.