IP Library Granted Patent US 11,296,192
Granted Patent B2
US 11,296,192 · App. 16/661,482 · Granted Apr 5, 2022

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

Inventors: Takeshi Tawara (Tsukuba, JP); Mina Ohse (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/1608H01L21/046H01L29/2003H01L29/868
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Quick Facts
Patent No.
US 11,296,192
App. No.
16/661,482
Granted
Apr 5, 2022
Kind
B2
Abstract

A silicon carbide semiconductor device includes, sequentially, a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the third semiconductor layer. A first electrode is provided on the first semiconductor layer, and a second electrode is provided on the fourth semiconductor layer. An impurity concentration of the second semiconductor layer is higher than that of the first semiconductor layer, and an impurity concentration of the third semiconductor layer is lower than that of the second semiconductor layer. The first semiconductor layer also contains, at a surface thereof in contact with the second semiconductor layer, a second impurity different from a first impurity that determines a conductivity type of the first semiconductor layer.

Claims (29)

1. A silicon carbide semiconductor device comprising:

a first semiconductor layer containing a first impurity, causing the first semiconductor layer to be of a first conductivity type, the first semiconductor layer having a first side and a second side opposite to each other;

a second semiconductor layer of the first conductivity type, provided on the first semiconductor layer, and having a first side and a second side opposite to each other, the second side of the second semiconductor layer facing the first side of the first semiconductor layer, the second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer;

a third semiconductor layer of the first conductivity type, provided on the first side of the second semiconductor layer, and having a first side and a second side opposite to each other, the second side of the third semiconductor layer facing the first side of the second semiconductor layer, the third semiconductor layer having an impurity concentration lower than that of the second semiconductor layer;

a fourth semiconductor layer of a second conductivity type, provided on the first side of the third semiconductor layer, and having a first side and a second side opposite to each other, the second side of the fourth semiconductor layer facing the first side of the third semiconductor layer;

a first electrode provided on the second side of the first semiconductor layer; and

a second electrode provided on the first side of the fourth semiconductor layer, wherein

the first semiconductor layer further contains, at a surface thereof in contact with the second semiconductor layer, in addition to the first impurity, a second impurity that has an impurity type different from that of the first impurity.

2. The silicon carbide semiconductor device according to claim 1 , wherein

the second semiconductor layer is a layer controlling carrier lifetime.

3. The silicon carbide semiconductor device according to claim 1 , wherein

the second semiconductor layer contains nitrogen as an impurity thereof, the impurity concentration of the second semiconductor layer being in a range from 1×10 18 to 2×10 19 /cm 3 .

4. The silicon carbide semiconductor device according to claim 3 , wherein

the second semiconductor layer contains, at a surface thereof in contact with the first semiconductor layer, the second impurity.

5. The silicon carbide semiconductor device according to claim 1 , wherein

the first impurity is nitrogen, and

the second impurity is vanadium, titanium, iron, chromium or boron.

6. A method of manufacturing a silicon carbide semiconductor device, the method comprising:

providing a first semiconductor layer of a first conductivity type that has a first side and a second side opposite to each other, the first semiconductor layer containing a first impurity that determines a conductivity type thereof;

ion implanting, at a surface of the first semiconductor layer, a second impurity that is of a type different from that of the first impurity, such that the surface contains both the first impurity and the second impurity;

forming, on the surface of the first semiconductor layer, a second semiconductor layer of the first conductivity type, the second semiconductor layer having a first side and a second side opposite to each other, the second side of the second semiconductor layer facing the first side of the first semiconductor layer, an impurity concentration of the second semiconductor layer being higher than that of the first semiconductor layer;

forming a third semiconductor layer of the first conductivity type on the first side of the second semiconductor layer, the third semiconductor layer having a first side and a second side opposite to each other, the second side of the third semiconductor layer facing the first side of the second semiconductor layer, an impurity concentration of the third semiconductor layer being lower than that of the second semiconductor layer;

forming a fourth semiconductor layer of a second conductivity type on the first side of the third semiconductor layer, the fourth semiconductor layer having a first side and a second side opposite to each other, the second side of the fourth semiconductor layer facing the first side of the third semiconductor layer;

forming a first electrode on the second side of the first semiconductor layer; and

forming a second electrode on the first side of the fourth semiconductor layer.

7. The method according to claim 6 , wherein

the first impurity is nitrogen,

the second impurity is vanadium, titanium, iron, chromium or boron, and

a dose amount of ion implantation of the second impurity is in a range from 1×10 16 to 1×10 20 /cm 3 , and an implantation depth of the second impurity is at least 0.3 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2019
From: TAWARA, TAKESHI; OHSE, MINA
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 050804/0556 →
Priority Claims (1)
JP JP2018-209294 · Nov 6, 2018 · national
Continuity (1)
Related Publication 20200144371A1 · May 7, 2020