Semiconductor devices and methods
Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.
1. A method comprising:
depositing a first sheet over a semiconductor substrate;
depositing a first semiconductor material over the first sheet;
depositing a second sheet over the first semiconductor material;
depositing a second semiconductor material over the second sheet;
patterning the first sheet, the first semiconductor material, the second sheet, and the second semiconductor material into a fin, wherein a topmost surface of the fin has both a first width and a second width in a top-down view, the first width being greater than the second width, and the first width being measured along a first direction parallel to a second direction that the second width is measured along;
removing the first sheet and the second sheet to form a first nanostructure from the first semiconductor material and a second nanostructure from the second semiconductor material;
depositing a gate dielectric layer to surround the first nanostructure and the second nanostructure; and
depositing a gate electrode around the gate dielectric layer.
2. The method of claim 1 , wherein the depositing the gate electrode comprises forming the gate electrode at least partially over a first corner of the first nanostructure.
3. The method of claim 2 , wherein after the depositing the gate dielectric layer, a gate spacer is adjacent to the gate dielectric layer and at least partially over a second corner of the first nanostructure, the second corner being adjacent to a portion of the fin with the second width.
4. The method of claim 2 , wherein the depositing the gate electrode comprises forming the gate electrode at least partially over a second corner of the first nanostructure.
5. The method of claim 4 , wherein after the depositing the gate dielectric layer, a gate spacer is adjacent to the gate dielectric layer and at least partially over the second corner of the first nanostructure, the second corner being adjacent to a portion of the fin with the first width.
6. The method of claim 1 , further comprising:
epitaxially growing a first source/drain region adjacent the first nanostructure, the first source/drain region having a third width; and
epitaxially growing a second source/drain region adjacent the first nanostructure, the second source/drain region having a fourth width different from the third width.
7. The method of claim 1 , wherein the first width is between about 8 nm and about 30 nm.
8. A method comprising:
forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising first layers having a first material and second layers having a second material different from the first material;
etching a pattern into the multilayer stack, a remainder of the multilayer stack comprising an active region separating a first side of the remainder of the multilayer stack from a second side of the remainder of the multilayer stack, wherein a topmost surface of the remainder of the multilayer stack has both a first width and a second width in a top-down view, wherein the second width is different from the first width, wherein the first width is measured along a first direction parallel to a second direction that the second width is measured along, the first width corresponding to the first side of the remainder of the multilayer stack and the second width corresponding to the second side of the remainder of the multilayer stack;
performing a wire release process to remove the first layers and form a stack of nanostructures, the stack of nanostructures having the first width at the first side and the second width at the second side;
depositing a gate dielectric layer around the stack of nanostructures; and
depositing a gate electrode surrounding each nanostructure within the stack of nanostructures.
9. The method of claim 8 further comprising forming a first source/drain region adjacent to the stack of nanostructures at the first side and forming a second source/drain region adjacent to the stack of nanostructures at the second side, the first source/drain region having a width that is greater than a width of the second source/drain region.
10. The method of claim 8 , wherein a difference between the first width and the second width is at most 8 nm.
11. The method of claim 8 , wherein one nanostructure within the stack of nanostructures comprises a first corner at the first side and the first corner is located at least partially beneath the gate electrode.
12. The method of claim 11 , wherein the one nanostructure comprises a second corner at the second side and the second corner is located at least partially beneath the gate electrode.
13. The method of claim 11 , wherein the one nanostructure comprises a second corner at the second side and the second corner is located at least partially beneath an interlayer dielectric, wherein the first width is larger than the second width.
14. The method of claim 11 , wherein the one nanostructure comprises a second corner at the second side and the second corner is located at least partially beneath an interlayer dielectric, wherein the first width is smaller than the second width.
15. A device comprising:
a gate dielectric over a substrate;
a gate electrode around the gate dielectric;
a vertical stack of nanostructures, each nanostructure of the vertical stack of nanostructures comprising an active region being surrounded by the gate dielectric, wherein a topmost surface of each of the active regions comprises:
a first channel width on a first side of the gate dielectric; and
a second channel width on a second side of the gate dielectric, the first channel width being greater than the second channel width, wherein the first channel width and the second channel width are measured along directions that are parallel to each other.
16. The device of claim 15 , wherein the first channel width is no greater than 16 nm larger than the second channel width.
17. The device of claim 15 , wherein a first nanostructure of the vertical stack of nanostructures comprises a first corner on the first side of the gate dielectric and a second corner on the second side of the gate dielectric.
18. The device of claim 17 further comprising:
a first gate spacer disposed adjacent the gate electrode on the first side of the gate dielectric; and
a second gate spacer disposed adjacent the gate electrode on the second side of the gate dielectric.
19. The device of claim 18 , wherein the first corner is disposed at least partially beneath the first gate spacer and the second corner is disposed at least partially beneath the gate electrode.
20. The device of claim 18 , wherein the first corner is disposed at least partially beneath the gate electrode and the second corner is disposed at least partially beneath the second gate spacer.