Low-power fractional analog PLL without feedback divider
An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.
1. A circuit comprising:
a phase lock loop (PLL) including:
a first PLL input;
a second PLL input; and
a voltage controlled oscillator (VCO) having a VCO output signal; and
a re-timer circuit having a re-timer output coupled to the second PLL input, and a re-timer input coupled to the VCO output signal.
2. The circuit of claim 1 , wherein:
the first PLL input is configured to receive a reference clock signal; and
the re-timer circuit is configured to receive the reference clock signal.
3. The circuit of claim 2 , wherein:
the re-timer circuit is configured to output a first re-timed clock signal in response to receiving the reference clock signal and the VCO output signal.
4. The circuit of claim 1 , wherein:
the PLL includes a feedback divider circuit having a feedback divider circuit input coupled to the VCO output signal and a feedback divider circuit output.
5. The circuit of claim 4 , further comprising:
a multiplexer having a first multiplexer input coupled to the re-timer output, a second multiplexer input coupled to the feedback divider circuit output, and a multiplexer output coupled to the PLL.
6. The circuit of claim 4 , wherein:
the feedback divider circuit includes a feedback buffer and a divider.
7. The circuit of claim 4 , wherein:
the feedback divider circuit is configured to be disabled.
8. The circuit of claim 7 , wherein:
the feedback divider circuit is configured to be disabled in response to a low power operation mode.
9. The circuit of claim 1 wherein:
the re-timer circuit is configured to output a plurality of re-timed clock signals on the re-timer output.
10. A method comprising:
receiving, by a phase lock loop (PLL), a power operation signal; and
in response to the power operation signal indicating low power operation:
disabling, by the PLL, a feedback divider circuit coupled to an output of a voltage controlled oscillator (VCO) of the PLL;
receiving, by the VCO, an error signal based on a re-timed clock signal, wherein the re-timed clock signal is based on a reference clock signal and the output of the VCO; and
outputting, by the VCO, a PLL output signal based on the error signal.
11. The method of claim 10 , wherein:
the re-timed clock signal includes:
a first re-timed clock signal based on the reference clock signal and the output of the VCO;
a second re-timed clock signal based on the reference clock signal and the output of the VCO;
a third re-timed clock signal based on the reference clock signal and the output of the VCO; and
a fourth re-timed clock signal based on the reference clock signal and the output of the VCO.
12. The method of claim 11 , wherein:
the first re-timed clock signal, the second re-timed clock signal, the third re-timed clock signal, and the fourth re-timed clock signal are each delayed by different numbers of clock cycles of the reference clock signal.
13. The method of claim 10 , wherein:
the feedback divider circuit is coupled a multiplexer.
14. The method of claim 13 , wherein:
the re-timed clock signal is output by the multiplexer to the PLL.
15. The method of claim 14 , wherein:
the error signal corresponds to a phase error of the PLL output signal.