Method and apparatus for symbol-error-rate (SER) based tuning of transmitters and receivers
Embodiments are disclosed for a sequence selective symbol checker for communication systems. An example method includes configuring a symbol checker of a receiver with first binary sequence data generated by a symbol generator of the receiver. The example method also includes comparing, using the symbol checker, second binary sequence data provided by a transmitter to the first binary sequence data to generate error count data related to a number of errors for symbols associated with the second binary sequence data. The example method also includes determining total count data related to a number of symbols associated with the first binary sequence data. The example method also includes determining error ratio data associated with the transmitter based on the error count data and the total count data.
1. A method for tuning based on symbol-error-rate, comprising:
configuring a symbol checker of a receiver with first binary sequence data generated by a symbol generator of the receiver;
comparing, using the symbol checker, second binary sequence data provided by a transmitter to the first binary sequence data to generate error count data related to a number of errors for symbols associated with the second binary sequence data;
determining total count data related to a number of symbols associated with the first binary sequence data;
determining error ratio data associated with the transmitter based on the error count data and the total count data; and
repeatedly tuning the transmitter in response to a determination that the error ratio data satisfies a defined criterion.
2. The method of claim 1 , wherein comparing the second binary sequence data to the first binary sequence data comprises comparing symbols of the second binary sequence data to symbols of the first binary sequence data using the symbol checker.
3. The method of claim 1 , further comprising:
tuning a look-up table of the transmitter based on the error ratio data.
4. The method of claim 1 , further comprising:
determining a number of error types for the symbol checker based on a type of coding for the second binary sequence data.
5. The method of claim 1 , further comprising:
synchronizing the first binary sequence data to the second binary sequence data based on a type of coding for the second binary sequence data.
6. The method of claim 1 , wherein determining the total count data comprises monitoring at least a current symbol of the first binary sequence data, a previous symbol of the first binary sequence data, and a future symbol of the first binary sequence data.
7. The method of claim 1 , wherein the first binary sequence data corresponds to an expected binary sequence for the second binary sequence data.
8. The method of claim 1 , wherein the error ratio data corresponds to a symbol-error-rate for the second binary sequence data.
9. The method of claim 1 , wherein the second binary sequence data is a pulse amplitude modulation signal.
10. The method of claim 1 , wherein the transmitter is a non-linear optical transmitter or a non-linear electrical transmitter.
11. An apparatus in a receiver comprising at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor:
configure a symbol checker of the receiver with first binary sequence data generated by a symbol generator of the receiver;
compare, based on the symbol checker, second binary sequence data provided by a transmitter to the first binary sequence data to generate error count data related to a number of errors for symbols associated with the second binary sequence data;
determine total count data related to a number of symbols associated with the first binary sequence data;
determine error ratio data associated with the transmitter based on the error count data and the total count data; and
repeatedly tune the transmitter in response to a determination that the error ratio data satisfies a defined criterion.
12. The apparatus of claim 11 , wherein the at least one memory and the computer program code are further configured to:
compare symbols of the second binary sequence data to symbols of the first binary sequence data using the symbol checker.
13. The apparatus of claim 11 , wherein the at least one memory and the computer program code are further configured to:
tune a look-up table of the transmitter based on the error ratio data.
14. The apparatus of claim 11 , wherein the at least one memory and the computer program code are further configured to:
determine a number of error types for the symbol checker based on a type of coding for the second binary sequence data.
15. The apparatus of claim 11 , wherein the at least one memory and the computer program code are further configured to:
synchronize the first binary sequence data to the second binary sequence data based on a type of coding for the second binary sequence data.
16. The apparatus of claim 11 , wherein the second binary sequence data is a pulse amplitude modulation signal.
17. An apparatus in a receiver comprising hardware logic circuitry configured to:
configure a symbol checker of the receiver with first binary sequence data generated by a symbol generator of the receiver;
compare, based on the symbol checker, second binary sequence data provided by a transmitter to the first binary sequence data to generate error count data related to a number of errors for symbols associated with the second binary sequence data;
determine total count data related to a number of symbols associated with the first binary sequence data;
determine error ratio data associated with the transmitter based on the error count data and the total count data; and
repeatedly tune the transmitter in response to a determination that the error ratio data satisfies a defined criterion.
18. The apparatus of claim 17 , wherein the hardware logic circuitry is further configured to:
tune a look-up table of the transmitter based on the error ratio data.
19. The apparatus of claim 17 , wherein the hardware logic circuitry is further configured to:
determine a number of error types for the symbol checker based on a type of coding for the second binary sequence data.
20. The apparatus of claim 17 , wherein the hardware logic circuitry is further configured to:
synchronize the first binary sequence data to the second binary sequence data based on a type of coding for the second binary sequence data.
21. A method for tuning based on symbol-error-rate, comprising:
configuring a symbol checker of a receiver with first binary sequence data generated by a symbol generator of the receiver;
synchronizing the first binary sequence data to second binary sequence data provided by a transmitter based on a type of coding for the second binary sequence data;
comparing, using the symbol checker, the second binary sequence data to the first binary sequence data to generate error count data related to a number of errors for symbols associated with the second binary sequence data;
determining total count data related to a number of symbols associated with the first binary sequence data; and
determining error ratio data associated with the transmitter based on the error count data and the total count data.
22. The method of claim 21 , further comprising:
tuning the transmitter based on the error ratio data.
23. The method of claim 21 , further comprising:
tuning a look-up table of the transmitter based on the error ratio data.