IP Library Granted Patent US 11,315,489
Granted Patent B1
US 11,315,489 · App. 17/233,877 · Granted Apr 26, 2022

Light emitting device driving circuit and related method

Inventors: Adnan Heganovic (Oxford, GB); Kohhei Tanaka (Sakai, JP); Ryo Yonebayashi (Sakai, JP); Masahito Sano (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
G09G3/3233G09G3/3283G09G2300/0819G09G2310/061G09G2320/045
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Quick Facts
Patent No.
US 11,315,489
App. No.
17/233,877
Granted
Apr 26, 2022
Kind
B1
Abstract

A pixel circuit includes a drive transistor configured to control an amount of current to a light emitting device during an emission phase depending upon a voltage applied to a control terminal of the drive transistor, the drive transistor having a first terminal and a second terminal. During a first phase, an anode of the light emitting device is set to a reference voltage and the first terminal of the drive transistor is set to a fixed data voltage such that the drive transistor is stressed with a fixed source-to-gate voltage to prevent a drift of a threshold voltage in the drive transistor thereby preventing a drift in screen brightness. During a second phase, the anode of the light emitting device is set to the reference voltage and the first terminal of the drive transistor is set to a voltage of the first power supply.

Claims (49)

1. A pixel circuit for a display device, the pixel circuit comprising:

a drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon a voltage applied to a control terminal of the drive transistor, the drive transistor having a first terminal and a second terminal;

a first transistor connected between a reference voltage and the control of the drive transistor;

a second switch transistor connected between the second terminal and the control terminal of the drive transistor;

a third switch transistor connected between a first power supply and the first terminal of the drive transistor;

a fourth switch transistor connected between a data line and the first terminal of the drive transistor;

a fifth switch transistor connected between the second terminal of the drive transistor and an anode of the light emitting device; and

a sixth switch transistor connected between the anode of the light emitting device and the reference voltage;

wherein, during a first phase having a fixed duration, the anode of the light emitting device is set to the reference voltage and the first terminal of the drive transistor is set to a fixed data voltage; and

wherein, during a second phase having a variable duration, the anode of the light emitting device is set to the reference voltage and the first terminal of the drive transistor is set to a voltage of the first power supply.

2. The pixel circuit of claim 1 , wherein:

during the first phase, a first emission pulse having a constant pulse width is applied to a control terminal of the sixth transistor to set the anode of the light emitting device to the reference voltage; and

during the first phase, a scan pulse is applied to a control terminal of the fourth transistor to set the first terminal of the drive transistor to the fixed data voltage.

3. The pixel circuit of claim 1 , wherein:

during the second phase, a second emission pulse having a variable pulse width is applied to a control terminal of the sixth transistor to set the anode of the light emitting device to the reference voltage, and to control a pulse width modulation (PWM) setting of the display device.

4. The pixel circuit of claim 1 , wherein during the first phase, the first terminal (S) of the drive transistor is set to the fixed data voltage such that the drive transistor is stressed with a fixed gate-to-source voltage to prevent a drift of a threshold voltage in the drive transistor thereby preventing a drift in screen brightness of the display device.

5. A pixel circuit for a display device, the pixel circuit comprising:

a drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon a voltage applied to a control terminal of the drive transistor, the drive transistor having a first terminal and a second terminal;

wherein, during a first phase having a fixed duration, an anode of the light emitting device is set to a reference voltage and the first terminal of the drive transistor is set to a fixed data voltage such that the drive transistor is stressed with a fixed source-to-gate voltage to prevent a drift of a threshold voltage in the drive transistor thereby preventing a drift in screen brightness of the display device; and

wherein, during a second phase having a variable duration, the anode of the light emitting device is set to the reference voltage and the first terminal of the drive transistor is set to a voltage of the first power supply.

6. The pixel circuit of claim 5 , further comprising a switch transistor connected between the reference voltage and the control of the drive transistor.

7. The pixel circuit of claim 5 , further comprising a switch transistor connected between the second terminal and the control terminal of the drive transistor.

8. The pixel circuit of claim 5 , further comprising a switch transistor connected between a first power supply and the first terminal of the drive transistor.

9. The pixel circuit of claim 5 , further comprising a switch transistor connected between a data line and the first terminal of the drive transistor.

10. The pixel circuit of claim 5 , further comprising a switch transistor connected between the second terminal of the drive transistor and an anode of the light emitting device.

11. The pixel circuit of claim 5 , further comprising a switch transistor connected between the anode of the light emitting device and the reference voltage.

12. The pixel circuit of claim 5 , wherein:

during the first phase, a first emission pulse having a constant pulse width is applied to a control terminal of a sixth transistor to set the anode of the light emitting device to the reference voltage; and

during the first phase, a scan pulse is applied to a control terminal of a fourth transistor to set the first terminal of the drive transistor to the fixed data voltage.

13. The pixel circuit of claim 5 , wherein:

during the second phase, a second emission pulse having a variable pulse width is applied to a control terminal of a sixth transistor to set the anode of the light emitting device to the reference voltage, and to control a pulse width modulation (PWM) setting of the display device.

14. A method of operating a pixel circuit for a display device, the method comprising:

providing the pixel circuit comprising:

a drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon a voltage applied to a control terminal of the drive transistor, the drive transistor having a first terminal and a second terminal;

a first transistor connected between a reference voltage and the control of the drive transistor;

a second switch transistor connected between the second terminal and the control terminal of the drive transistor;

a third switch transistor connected between a first power supply and the first terminal of the drive transistor;

a fourth switch transistor connected between a data line and the first terminal of the drive transistor;

a fifth switch transistor connected between the second terminal of the drive transistor and an anode of the light emitting device; and

a sixth switch transistor connected between the anode of the light emitting device and the reference voltage;

performing a first phase having a fixed duration, during which the anode of the light emitting device is set to the reference voltage and the first terminal of the drive transistor is set to a fixed data voltage; and

performing a second phase having a variable duration, during which the anode of the light emitting device is set to the reference voltage and the first terminal of the drive transistor is set to a voltage of the first power supply.

15. The method of claim 14 , wherein the first phase is an anode reset and on bias stress phase.

16. The method of claim 15 , wherein:

during the anode reset and on bias stress phase, a first emission pulse having a constant pulse width is applied to a control terminal of the sixth transistor to set the anode of the light emitting device to the reference voltage; and

during the anode reset and on bias stress phase, a scan pulse is applied to a control terminal of the fourth transistor to set the first terminal of the drive transistor to the fixed data voltage.

17. The method of claim 14 , wherein the second phase is an anode reset only phase.

18. The method of claim 17 , wherein, during the anode reset only phase, a second emission pulse having a variable pulse width is applied to a control terminal of the sixth transistor to set the anode of the light emitting device to the reference voltage, and to control a pulse width modulation (PWM) setting of the display device.

19. The method of claim 14 , wherein, during the first phase, the first terminal (S) of the drive transistor is set to a fixed data voltage such that the drive transistor is stressed with a fixed gate-to-source voltage to prevent a drift of a threshold voltage in the drive transistor to prevent a drift in screen brightness of the display device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2021
From: HEGANOVIC, ADNAN; TANAKA, KOHHEI; YONEBAYASHI, RYO; SANO, MASAHITO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 055957/0968 →
Cited By (2)
US 12,354,519 US 12,640,100