Reed-Solomon code soft-decision decoding method and device

1. A Reed-Solomon code soft-decision decoding device, comprising:

a syndrome generation circuit configured to generate a syndrome from a codeword;

a key equation solver circuit configured to generate an error location polynomial and an error evaluation polynomial based on the syndrome;

a Chien-search & error-evaluator circuit configured to determine a location and magnitude of an error in the codeword based on the error location polynomial and the error evaluation polynomial;

a decoding error detection circuit configured to determine whether decoding on the codeword is successful or failed based on the location and magnitude of the error; and

an erasure control circuit configured to determine whether a number of errors in the codeword is odd or even, and to provide the key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by the decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.

2. The Reed-Solomon code soft-decision decoding device of claim 1 , wherein the erasure control circuit receives the syndrome from the syndrome generation circuit and determines whether the number of errors in the codeword is odd or even by using characteristics of the syndrome.

3. The Reed-Solomon code soft-decision decoding device of claim 2 , wherein, when a number of bits each having a value of 1 in the syndrome is odd, the erasure control circuit determines the number of errors to be odd, and when the number of bits each having the value of 1 in the syndrome is even, the erasure control circuit determines the number of errors to be even.

4. The Reed-Solomon code soft-decision decoding device of claim 1 , wherein, when the number of errors is determined to be odd and the decoding failure is detected, the erasure control circuit provides, as the first erasure pattern, 2+4j erasure patterns to the key equation solver circuit, j being an integer equal to or more than 0.

5. The Reed-Solomon code soft-decision decoding device of claim 4 , wherein, when the number of errors is determined to be even and the decoding failure is detected, the erasure control circuit provides, as the second erasure pattern, 4k erasure patterns to the key equation solver circuit, k being a positive integer.

6. The Reed-Solomon code soft-decision decoding device of claim 5 , wherein the erasure control circuit provides the key equation solver circuit with the 2+4j erasure patterns or the 4k erasure patterns in an order in which a symbol with low reliability among symbols in the codeword is preferentially erased.

7. The Reed-Solomon code soft-decision decoding device of claim 1 , wherein the key equation solver circuit calculates the error location polynomial and the error evaluation polynomial based on the syndrome and 2+4j erasure patterns that are the first erasure pattern or based on the syndrome and 4k erasure patterns that are the second erasure pattern.

8. A Reed-Solomon code soft-decision decoding method, comprising:

generating a syndrome from a codeword;

generating an error location polynomial and an error evaluation polynomial based on the syndrome;

determining a location and magnitude of an error in the codeword based on the error location polynomial and the error evaluation polynomial;

determining whether decoding on the codeword is successful or failed based on the location and magnitude of the error; and

determining whether a number of errors in the codeword is odd or even, and performing decoding on the codeword based on the syndrome and a first erasure pattern or based on the syndrome and a second erasure pattern according to a result of the determining when a decoding failure is detected, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.

9. The Reed-Solomon code soft-decision decoding method of claim 8 , wherein, in determining whether the number of errors in the codeword is odd or even, a number of symbol errors in the syndrome is determined to be odd or even by using characteristics of the syndrome.

10. The Reed-Solomon code soft-decision decoding method of claim 9 , wherein, in determining whether the number of errors in the codeword is odd or even, when a number of bits each having a value of 1 in the syndrome is odd, the number of symbol errors is determined to be odd, and when the number of bits each having the value of 1 in the syndrome is even, the number of symbol errors is determined to be even.

11. The Reed-Solomon code soft-decision decoding method of claim 8 , wherein performing the decoding based on the syndrome and the first erasure pattern comprises:

applying, as the first erasure pattern, 2+4j erasure patterns to the codeword.

12. The Reed-Solomon code soft-decision decoding method of claim 11 , wherein performing the decoding based on the syndrome and the second erasure pattern comprises:

applying, as the second erasure pattern, 4k erasure patterns to the codeword.

13. The Reed-Solomon code soft-decision decoding method of claim 12 , wherein the 2+4j erasure patterns or the 4k erasure patterns are applied to the codeword in an order in which a symbol with low reliability among symbols in the codeword is preferentially erased.

14. A semiconductor device, comprising:

a memory cell array configured to store a codeword; and

a Reed-Solomon code soft-decision decoding device configured to read the codeword from the memory cell array, decode the codeword, and output error-corrected data corresponding to the codeword,

wherein the Reed-Solomon code soft-decision decoding device comprises:

a syndrome generation circuit configured to generate a syndrome from the codeword;

a key equation solver circuit configured to generate an error location polynomial and an error evaluation polynomial based on the syndrome;

a Chien-search & error-evaluator circuit configured to determine a location and magnitude of an error in the codeword based on the error location polynomial and the error evaluation polynomial;

a decoding error detection circuit configured to determine whether decoding on the codeword is successful or failed based on the location and magnitude of the error; and

an erasure control circuit configured to determine whether a number of errors in the codeword is odd or even, and to provide the key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by the decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.

15. The semiconductor device of claim 14 , wherein the erasure control circuit receives the syndrome from the syndrome generation circuit and determines whether the number of errors in the codeword is odd or even by using characteristics of the syndrome.

16. The semiconductor device of claim 15 , wherein, when a number of bits each having a value of 1 in the syndrome is odd, the erasure control circuit determines the number of errors to be odd, and when the number of bits each having the value of 1 in the syndrome is even, the erasure control circuit determines the number of errors to be even.

17. The semiconductor device of claim 14 , wherein, when the number of errors is determined to be odd and the decoding failure is detected, the erasure control circuit provides, as the first erasure pattern, 2+4j erasure patterns to the key equation solver circuit.

18. The semiconductor device of claim 17 , wherein, when the number of errors is determined to be even and the decoding failure is detected, the erasure control circuit provides, as the second erasure pattern, 4k erasure patterns to the key equation solver circuit.

19. The semiconductor device of claim 18 , wherein the erasure control circuit provides the key equation solver circuit with the 2+4j (erasure patterns or the 4k erasure patterns in an order in which a symbol with low reliability among symbols in the codeword is preferentially erased.