IP Library Granted Patent US 11,335,641
Granted Patent B2
US 11,335,641 · App. 16/648,332 · Granted May 17, 2022

Microelectronic assemblies

Inventors: Aleksandar Aleksov (Chandler, AZ); Johanna M. Swan (Scottsdale, AZ)
Assignee: Intel Corporation
H01L23/5386H01L23/13H01L23/3675H01L23/49816H01L23/5383H01L23/5389H01L24/17H01L25/0652H01L25/16H01L24/32H01L24/73H01L2224/16145H01L2224/16227H01L2224/17181H01L2224/32245H01L2224/73253H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06589
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Quick Facts
Patent No.
US 11,335,641
App. No.
16/648,332
Granted
May 17, 2022
Kind
B2
Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

Claims (57)

1. A microelectronic assembly, comprising:

a package substrate including:

a dielectric material having a first surface and an opposing second surface,

a first photodefinable material on at least a portion of the second surface,

a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material, and wherein the second photodefinable material provides a sidewall of a recess,

first conductive contacts and second conductive contacts,

first openings through the first photodefinable material and the second photodefinable material exposing the first conductive contacts, and

second openings through the first photodefinable material exposing the second conductive contacts, wherein the second openings are offset by a nonzero amount from being centered in the recess.

2. The microelectronic assembly of claim 1 , wherein the first conductive contacts have a pitch that is larger than a pitch of the second conductive contacts.

3. A microelectronic assembly, comprising:

a package substrate including:

a dielectric material having a first surface and an opposing second surface,

a first photodefinable material on at least a portion of the second surface,

a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material,

first conductive contacts and second conductive contacts,

first openings through the first photodefinable material and the second photodefinable material exposing the first conductive contacts, and

second openings through the first photodefinable material exposing the second conductive contacts,

a first die conductively coupled to at least some of the first conductive contacts; and

a second die conductively coupled to the second conductive contacts, wherein the first die extends at least partially over the second die.

4. A microelectronic assembly, comprising:

a package substrate including:

a dielectric material having a first surface and an opposing second surface,

a first photodefinable material on at least a portion of the second surface,

a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material,

first conductive contacts and second conductive contacts,

first openings through the first photodefinable material and the second photodefinable material that expose the first conductive contacts, and

second openings through the first photodefinable material that expose the second conductive contacts,

a first die conductively coupled to at least some of the first conductive contacts; and

a second die conductively coupled to the second conductive contacts, wherein the second die has a first surface and an opposing second surface, conductive contacts at the first surface of the second die are conductively coupled to the second conductive contacts, and conductive contacts at the second surface of the second die are conductively coupled to conductive contacts of the first die.

5. The microelectronic assembly of claim 4 , further comprising:

a third die conductively coupled to at least some of the first conductive contacts, wherein conductive contacts at the second surface of the second die are conductively coupled to conductive contacts of the third die.

6. A microelectronic assembly, comprising:

a package substrate having a first surface and an opposing second surface, wherein the package substrate includes:

a dielectric material at the second surface, wherein the dielectric material includes a recess, and sidewalls of the recess are undercut,

first conductive contacts and second conductive contacts,

first openings through the dielectric material exposing the first conductive contacts, and

second openings through the dielectric material exposing the second conductive contacts at a bottom of the recess, and

a die at least partially in the recess and conductively coupled to the second conductive contacts.

7. The microelectronic assembly of claim 6 , wherein the first conductive contacts have a pitch between 80 microns and 200 microns and the second conductive contacts have a pitch between 20 microns and 80 microns.

8. The microelectronic assembly of claim 6 , further comprising:

a circuit board coupled to the package substrate.

9. The microelectronic assembly of claim 6 , wherein the package substrate is included in a handheld computing device or a server.

10. A microelectronic assembly, comprising:

a package substrate having a first surface and an opposing second surface, wherein the package substrate includes a dielectric material at the second surface, the dielectric material includes a recess, and corners of a top view of the recess have a rounding radius that is less than 10 microns.

11. The microelectronic assembly of claim 10 , wherein the dielectric material is a first dielectric material, the package substrate includes a second dielectric material, the second dielectric material has a first surface and an opposing second surface, and the first dielectric material includes:

a first photodefinable material on at least a portion of the second surface of the second dielectric material, and

a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

12. The microelectronic assembly of claim 10 , wherein one of the first photodefinable material or the second photodefinable material has a negative tone, and an other of the first photodefinable material or the second photodefinable material has a positive tone.

13. The microelectronic assembly of claim 10 , wherein the first photodefinable material or the second photodefinable material includes silica in an amount of 20 percent to 30 percent by weight.

14. The microelectronic assembly of claim 10 , wherein the first photodefinable material or the second photodefinable material includes silica in an amount of 70 percent to 90 percent by weight.

15. The microelectronic assembly of claim 1 , further comprising:

solder material in the first openings and in the second openings.

16. The microelectronic assembly of claim 1 , further comprising:

a first die conductively coupled to at least some of the first conductive contacts; and

a second die conductively coupled to the second conductive contacts.

17. The microelectronic assembly of claim 10 , wherein the first photodefinable material includes silica in an amount of 70 percent to 90 percent by weight, and the second photodefinable material includes silica in an amount of 20 percent to 30 percent by weight.

18. The microelectronic assembly of claim 1 , wherein the second die is conductively coupled to the first die by metal-to-metal interconnects.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2020
From: ALEKSOV, ALEKSANDAR; SWAN, JOHANNA M.
To: INTEL CORPORATION
Reel/Frame 052150/0777 →
Continuity (1)
Related Publication 20200219816A1 · Jul 9, 2020