Reconfigurable processing-in-memory logic
An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
1. A system, comprising:
a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines;
a logic array coupled to the memory array, the logic array to implement a configurable logic controlling the plurality of memory cells, wherein the configurable logic comprises a first pull network that is connected via a logical inverter to a second pull network; and
a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
2. The system of claim 1 , wherein the control block is further to:
pre-charge a selected bitline of the plurality of bitlines, wherein at least one wordline of the plurality of wordlines is open during the pre-charge operation; and
evaluate, using the configurable logic, a row of memory cells addressed by a selected wordline.
3. The system of claim 2 , wherein the control block is further to:
store, in an available memory cell accessible via a wordline of the plurality of wordlines, a state of the selected bitline.
4. The system of claim 1 , wherein the first pull network is provided by one of: a pull-up network (PUN) or a pull-down network (PDN).
5. The system of claim 1 , wherein the configurable logic is controlled by one or more inputs received from the control block.
6. The system of claim 1 , wherein the configurable logic is controlled by one or more inputs received from the memory array.
7. The system of claim 1 , wherein the configurable logic is controlled by one or more inputs received from an external source.
8. The system of claim 1 , wherein the system further comprises a sense amplifier array, and wherein the logic array is integrated with the sense amplifier array.
9. The system of claim 1 , wherein the computational pipeline comprises a systolic array.
10. The system of claim 1 , implemented as a system-on-chip, the system further comprising:
at least one processing core; and
at least one input/output (I/O) interfaces.
11. A system, comprising:
a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines, the memory array to implement configurable logic controlling the plurality of memory cells, wherein the configurable logic comprises a first pull network that is connected via a logical inverter to a second pull network; and
a control block coupled to the memory array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
12. The system of claim 11 , wherein the control block is further to:
pre-charge a selected bitline of the plurality of bitlines, wherein at least one wordline of the plurality of wordlines is open during the pre-charge operation; and
evaluate, using the configurable logic, a row of memory cells addressed by a selected wordline.
13. The system of claim 12 , wherein the control block is further to:
store, in an available memory cell accessible via a wordline of the plurality of wordlines, a state of the selected bitline.
14. The system of claim 11 , wherein the control block is further to:
pre-charge a selected bitline of the plurality of bitlines, wherein a first wordline of the plurality of wordlines is open during the pre-charge operation;
pre-charge a second wordline using a voltage level specified by an input supplied by the control block;
evaluate, using the configurable logic, a row of memory cells addressed by a selected wordline.
15. The system of claim 11 , wherein the first pull network is provided by one of: a pull-up network (PUN) or a pull-down network (PDN).
16. A method, comprising:
implementing a configurable logic by storing data in a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines, wherein the configurable logic comprises a first pull network that is connected via a logical inverter to a second pull network;
activating, by a control block coupled to the memory array, a selected bitline of the plurality of bitlines;
pre-charging the selected bitline, wherein at least one wordline of the plurality of wordlines is open during the pre-charge operation; and
evaluating, using the configurable logic, a row of memory cells addressed by a selected wordline.
17. The method of claim 16 , further comprising:
storing, in an available memory cell accessible via a wordline of the plurality of wordlines, a state of the selected bitline.
18. The method of claim 16 , wherein the first pull network is provided by one of: a pull-up network (PUN) or a pull-down network (PDN).