Memory device and operation method thereof
Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.
1. An operation method of a memory device including a plurality of word lines, the operation method comprising:
performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group of the word lines and applying an unselected word line voltage on a first unselected word line group of the word lines, and in a second loop, applying the selected word line voltage on a second selected word line group of the word lines and applying the unselected word line voltage on a second unselected word line group of the word lines, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group;
performing an erase operation on the word lines; and
performing a programming operation on the word lines.
2. The operation method according to claim 1 , wherein
in an unselected word line pre-on phase of the first loop, the selected word line voltage is transited to a first selected word line voltage and the unselected word line voltage is transited to a logic high level; and
in a pre-fill phase of the first loop, the selected word line voltage is transited from the first selected word line voltage to a second selected word line voltage and the unselected word line voltage is kept at the logic high level.
3. The operation method according to claim 2 , wherein the first selected word line voltage is higher than 0V but lower than the second selected word line voltage.
4. The operation method according to claim 3 , wherein the second selected word line voltage is equal to a programming voltage; and the logic high level of the unselected word line voltage is about a difference value between the programming voltage and a first predetermined voltage.
5. The operation method according to claim 1 , wherein
in an unselected word line pre-on phase of the first loop, the selected word line voltage is kept at a logic low level and the unselected word line voltage is transited to a first unselected word line voltage; and
in a pre-fill phase of the first loop, the selected word line voltage is transited to a logic high level and the unselected word line voltage is transited from the first unselected word line voltage to a second unselected word line voltage, wherein the unselected word line pre-on phase and the pre-fill phase are partially overlapped.
6. The operation method according to claim 5 , wherein the first unselected word line voltage is higher than 0V but lower than the second unselected word line voltage.
7. The operation method according to claim 6 , wherein the second unselected word line voltage is about a difference value between a programming voltage and a first predetermined voltage.
8. The operation method according to claim 1 , wherein the word lines includes an odd word line group and an even word line group, the first selected word line group includes any one of the odd word line group and the even word line group, and the second selected word line group includes the other one of the odd word line group and the even word line group.
9. The operation method according to claim 1 , wherein
the word lines includes a first word line group and a second word line group, the first word line group includes a plurality of first word line sub-groups each including adjacent continuous “i” (“i” being a positive integer) word line(s) while the second word line group includes a plurality of second word line sub-groups each including adjacent continuous “j” (“j” being a positive integer) word line(s), the first word line sub-groups and the second word line sub-groups are interleaving to each other; and
the first selected word line group includes any one of the first word line group and the second word line group while the first unselected word line group includes the other one of the first word line group and the second word line group.
10. The operation method according to claim 1 , wherein the word lines are “N” word lines (“N” being a positive integer), the first selected word line group includes “k” (“k” being a positive integer) adjacent continuous word line(s) and the second word line group includes the other “N−k” word line(s).
11. A memory device including:
a controller; and
a memory array coupled to the controller, the memory array including a plurality of word lines,
wherein the controller is configured for:
performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group of the word lines and applying an unselected word line voltage on a first unselected word line group of the word lines, and in a second loop, applying the selected word line voltage on a second selected word line group of the word lines and applying the unselected word line voltage on a second unselected word line group of the word lines, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group;
performing an erase operation on the word lines; and
performing a programming operation on the word lines.
12. The memory array according to claim 11 , wherein
in an unselected word line pre-on phase of the first loop, the selected word line voltage is transited to a first selected word line voltage and the unselected word line voltage is transited to a logic high level; and
in a pre-fill phase of the first loop, the selected word line voltage is transited from the first selected word line voltage to a second selected word line voltage and the unselected word line voltage is kept at the logic high level.
13. The memory array according to claim 12 , wherein the first selected word line voltage is higher than 0V but lower than the second selected word line voltage.
14. The memory array according to claim 13 , wherein the second selected word line voltage is equal to a programming voltage; and the logic high level of the unselected word line voltage is about a difference value between the programming voltage and a first predetermined voltage.
15. The memory array according to claim 11 , wherein
in an unselected word line pre-on phase of the first loop, the selected word line voltage is kept at a logic low level and the unselected word line voltage is transited to a first unselected word line voltage; and
in a pre-fill phase of the first loop, the selected word line voltage is transited to a logic high level and the unselected word line voltage is transited from the first unselected word line voltage to a second unselected word line voltage, wherein the unselected word line pre-on phase and the pre-fill phase are partially overlapped.
16. The memory array according to claim 15 , wherein the first unselected word line voltage is higher than 0V but lower than the second unselected word line voltage.
17. The memory array according to claim 16 , wherein the second unselected word line voltage is about a difference value between a programming voltage and a first predetermined voltage.
18. The memory array according to claim 11 , wherein the word lines includes an odd word line group and an even word line group, the first selected word line group includes any one of the odd word line group and the even word line group, and the second selected word line group includes the other one of the odd word line group and the even word line group.
19. The memory array according to claim 11 , wherein
the word lines includes a first word line group and a second word line group, the first word line group includes a plurality of first word line sub-groups each including adjacent continuous “i” (“i” being a positive integer) word line(s) while the second word line group includes a plurality of second word line sub-groups each including adjacent continuous “j” (“j” being a positive integer) word line(s), the first word line sub-groups and the second word line sub-groups are interleaving to each other; and
the first selected word line group includes any one of the first word line group and the second word line group while the first unselected word line group includes the other one of the first word line group and the second word line group.
20. The memory array according to claim 11 , wherein the word lines are “N” word lines (“N” being a positive integer), the first selected word line group includes “k” (“k” being a positive integer) adjacent continuous word line(s) and the second word line group includes the other “N−k” word line(s).