Methods and systems for reducing downtime from system management mode in a computer system
A system and method for shortening the system management mode when a fault occurs in hardware component in a computer system is disclosed. The computer system has hardware components that may have faults. Notification of an error in one of the hardware components is received through RAS silicon on a processing unit. The error is detected from the hardware component by a system management interrupt handler executed by a bootstrap processor core. The error data is logged into a system error log via a system control interrupt handler executed by the processing unit. The system management mode is avoided during the logging of the error data. This prevents other processor cores being suspended from the system management mode.
1. A computer system comprising:
a basic input output system (BIOS) chip;
a processor unit having a bootstrap core executing a system management interrupt handler and a system control interrupt handler stored in the BIOS chip, and silicon for receiving error information;
a hardware component coupled to the processor unit, the hardware component sending error information to the silicon; and
a management controller including a system error log, the management controller coupled to the processor unit, wherein the bootstrap core executes the system control interrupt handler to avoid a system management mode, and wherein the system control interrupt handler logs an error of the hardware component in the system error log.
2. The system of claim 1 , wherein the management controller is a baseboard management controller.
3. The system of claim 1 , wherein the computer system is a server.
4. The system of claim 1 , wherein the bootstrap core enters the system management mode and executes the system management mode interrupt handler to detect the error, and wherein the system management interrupt handler exits the system management mode after detecting the error.
5. The system of claim 1 , wherein the hardware component is one of a peripheral component interface express (PCIe) device, a dual in line memory module, a hard disk drive, a universal serial bus device, a serial peripheral interface (SPI) device, and system management bus (SMBUS) device.
6. The system of claim 1 , wherein the processor unit includes a plurality of processor cores including the bootstrap core.
7. The system of claim 1 , wherein the processor unit includes a south bridge chip including the silicon, and wherein the silicon performs reliability-availability-serviceable (RAS) features.
8. The system of claim 1 , wherein the system control interrupt handler detects the error.
9. The system of claim 8 , wherein the system control interrupt handler is initiated by a signal from a general purpose input output (GPIO) controller.
10. The system of claim 8 , wherein the system control interrupt handler is initiated directly from the silicon triggering the system control interrupt.
11. A method of operating a computer system comprising:
receiving notification of an error in a hardware component through silicon on a processing unit;
detecting the error from the hardware component; and
logging error data of the hardware component into a system error log managed by a management controller via a system control interrupt handler executed by a processor core of the processing unit, wherein a system management mode is avoided during the logging of the error data.
12. The method of claim 11 , wherein the error detection is performed via a system management interrupt handler, and wherein the computer system enters into a system management mode during the error detection and exits the system management mode when the error data is logged.
13. The method of claim 11 , wherein the management controller is a baseboard management controller.
14. The method of claim 11 , wherein the computer system is a server.
15. The method of claim 11 , wherein the processor core is one of a plurality of processor cores operable to process threads while the error logging occurs.
16. The method of claim 11 , wherein the hardware component is one of a peripheral component interface express (PCIe) device, a dual in line memory module, a hard disk drive, a universal serial bus device, a serial peripheral interface (SPI) device, and system management bus (SMBUS) device.
17. The method of claim 11 , wherein the processor unit includes a south bridge chip including the silicon, and wherein the silicon performs reliability-availability-serviceable (RAS) features.
18. The method of claim 11 , wherein the error detection is performed via a system control interrupt handler executed by the processor core.
19. The method of claim 18 , wherein the system control interrupt handler is initiated by a signal from a general purpose input output (GPIO) controller.
20. The method of claim 18 , wherein the system control interrupt handler is initiated directly from the silicon triggering the system control interrupt.