Recessed metal interconnects to mitigate EPE-related via shorting
Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.
1. An interconnect structure, comprising:
a semiconductor substrate;
an interlayer dielectric (ILD) over the semiconductor substrate;
an interconnect layer over the ILD, wherein the interconnect layer comprises a first interconnect and a second interconnect; and
an electrically insulating plug that separates the first interconnect and the second interconnect, wherein an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer, and wherein the electrically insulating plug is not vertically overlapping with the interconnect layer.
2. The interconnect structure of claim 1 , wherein the uppermost surface of the interconnect layer is has a roughness that is less than a roughness of an etched metal surface of the interconnect layer.
3. The interconnect structure of claim 2 , wherein the roughness of the uppermost surface of the interconnect layer is 0.5 nm/σ or less.
4. The interconnect structure of claim 1 , wherein the uppermost surface of the electrically insulating plug is at least 10 nm above the uppermost surface of the interconnect layer.
5. The interconnect structure of claim 4 , wherein the uppermost surface of the electrically insulating plug is between 15 nm and 20 nm above the uppermost surface of the interconnect layer.
6. The interconnect structure of claim 1 , further comprising:
a liner over the interconnect layer, wherein the liner separates the electrically insulating plug from the first interconnect and the second interconnect.
7. The interconnect structure of claim 1 , wherein the electrically insulating plug is selective to SiO x and SiN etches.
8. The interconnect structure of claim 7 , wherein the electrically insulating plug comprises SiC.
9. The interconnect structure of claim 7 , wherein the electrically insulating plug comprises a metal oxide.
10. The interconnect structure of claim 9 , wherein the electrically insulating plug comprises ZrO 2 , HfO 2 , or Al 2 O 3 .
11. A semiconductor device, comprising:
a transistor device formed on a semiconductor substrate;
a plurality of interlayer dielectrics (ILDs) disposed over the semiconductor substrate;
a plurality of interconnect layers in the plurality of ILDs, wherein at least one of the interconnect layers is electrically coupled to the transistor device; and
a plurality of electrically isolating plugs, wherein each electrically isolating plug intersects an interconnect layer, and wherein an uppermost surface of each electrically isolating plug is above an uppermost surface of the interconnect layer the electrically isolating plug is intersecting, and wherein each electrically insulating plug is not vertically overlapping with the interconnect layer.
12. The semiconductor device of claim 11 , wherein the uppermost surface of the interconnect layer is has a roughness that is 0.5 nm/σ or less.
13. The semiconductor device of claim 11 , wherein the uppermost surface of the electrically insulating plug is at least 10 nm above the uppermost surface of the interconnect layer.
14. The semiconductor device of claim 11 , further comprising:
a liner over the interconnect layer, wherein the liner separates the electrically insulating plug from the interconnect layer.