Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection

1. A system, comprising:

a phase detector;

a first digital-to-time converter (DTC) having a signal input, a control input, and an output, wherein the signal input of the first DTC is configured to receive a reference signal, and the output of the first DTC is coupled to a first input of the phase detector;

a second DTC having a signal input, a control input, and an output, wherein the signal input of the second DTC is configured to receive a feedback signal, and the output of the second DTC is coupled to a second input of the phase detector; and

a decoder having an input, a first output, and a second output, wherein the input of the decoder is configured to receive a delta-sigma modulator (DSM) error signal, the first output of the decoder is coupled to the control input of the first DTC, and the second output of the decoder is coupled to the control input of the second DTC.

2. The system of claim 1 , wherein the decoder is configured to:

output a first code at the first output;

output a second code at the second output; and

adjust the first code and the second code in opposite directions based on the DSM error signal.

3. The system of claim 2 , wherein:

the first DTC is configured to set a time delay of the first DTC based on the first code; and

the second DTC is configured to set a time delay of the second DTC based on the second code.

4. The system of claim 2 , wherein the decoder is configured to adjust the first code and the second code by an approximately equal amount in the opposite directions based on the DSM error signal.

5. The system of claim 1 , wherein the decoder is configured to adjust a time delay of the first DTC and a time delay of the second DTC in opposite directions based on the DSM error signal.

6. The system of claim 1 , further comprising:

a frequency divider coupled between the signal input of the second DTC and a voltage-controlled oscillator (VCO); and

a DSM coupled to the frequency divider and the input of the decoder, wherein the DSM is configured to:

modulate a divider of the frequency divider based on a frequency control signal; and

generate the DSM error signal, wherein the DSM error signal indicates a quantization error of the DSM.

7. The system of claim 6 , further comprising:

a charge pump coupled to the phase detector; and

a loop filter coupled between the charge pump and the VCO.

8. The system of claim 7 , further comprising a mixer coupled to the VCO.

9. The system of claim 8 , further comprising a power amplifier coupled to the mixer.

10. The system of claim 8 , further comprising a low noise amplifier coupled to the mixer.

11. The system of claim 1 , further comprising a reference signal generator coupled to the signal input of the first DTC.

12. The system of claim 1 , further comprising a low dropout (LDO) regulator coupled to the first DTC and the second DTC.

13. A method of quantization noise cancellation in a phase-locked loop (PLL), wherein the PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal, the method comprising:

delaying the reference signal by a first time delay;

delaying the feedback signal by a second time delay;

receiving a delta-sigma modulator (DSM) error signal; and

adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.

14. The method of claim 13 , further comprising:

dividing a frequency of an oscillator signal by a divider to generate the feedback signal; and

modulating the divider using a DSM, wherein the DSM error signal indicates a quantization error of the DSM.

15. The method of claim 13 , wherein adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal comprises adjusting the first time delay and the second time delay by an approximately equal amount in the opposite directions based on the DSM error signal.

16. The method of claim 13 , wherein:

delaying the reference signal by the first time delay comprises delaying the reference signal by the first time delay based a first code using a first digital-to-time converter (DTC);

delaying the feedback signal by the second time delay comprises delaying the feedback signal by the second time delay based a second code using a second DTC; and

adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal comprises adjusting the first code and the second code in opposite directions based on the DSM error signal.

17. An apparatus, comprising:

means for detecting a phase error between a reference signal and a feedback signal;

means for delaying the reference signal by a first time delay;

means for delaying the feedback signal by a second time delay; and

means for adjusting the first time delay and the second time delay in opposite directions based on a delta-sigma modulator (DSM) error signal.

18. The apparatus of claim 17 , wherein the means for adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal comprises means for adjusting the first time delay and the second time delay by an approximately equal amount in the opposite directions based on the DSM error signal.

19. The apparatus of claim 17 , further comprising means for dividing a frequency of an oscillator signal by a divider to generate the feedback signal.

20. The apparatus of claim 19 , further comprising a DSM configured to:

modulate the divider based on a frequency control signal; and

generate the DSM error signal based on a quantization error of the DSM.