Wireless power system
A method of over-current protection in a wireless power receiver operating in a high-power mode includes digitally receiving an output current signal, generating an OC INT signal if the output current signal is greater than a current limit value, and if the OC INT signal is generated, transmitting Count A number of End Power Transfer (EPT) packets. If wireless power transmission has not stopped, transmitting Count C number of Control Error Packets (CEPs) with Value B. If wireless power transmission has not reduced such that the output current IL is below the current limit value, then enabling an LDO current limit circuit in a power block of the wireless power receiver. In a low-power mode, the receiver enables a hardware over-current circuit that generates an OC INT signal when the output current exceeds a current limit.
1. A method of over-current protection in a wireless power receiver, comprising:
in a high-power mode,
receiving a digitized output current signal from an analog-to-digital converter that receives and digitizes an output current of a rectifier of the wireless power receiver to provide the digitized output current signal;
comparing the digitized output current signal with a current limit value;
generating an over-current interrupt (OC INT) signal if the digitized output current signal is greater than the current limit value;
if the OC INT signal is not generated, then returning to receiving the digitized output current signal; and
if the OC INT signal is generated,
transmitting Count A number of End Power Transfer (EPT) packets to a wireless power transmitter, then
determining whether wireless power transmission has stopped,
if the wireless power transmission has stopped, then stop,
if the wireless power transmission has not stopped, transmitting Count C number of Control Error Packets (CEPs) with value B to the wireless power transmitter, and
if wireless power transmission has not reduced such that the output current IL is below the current limit value, then enabling an low-dropout regulator (LDO) current limit circuit in a power block of the wireless power receiver.
2. The method of claim 1 , wherein Count A is a value between 0 and FFh, wherein a value A=0 disables transmission of EPT packets and a hexadecimal value A=FFh indicates repeated transmissions of the EPT packets.
3. The method of claim 1 , wherein Count A is set to a A default value.
4. The method of claim 1 , wherein Count A is set by a user input to the wireless power receiver.
5. The method of claim 1 , wherein Count C is a value between 0 and hexadecimal FFh wherein a value of C=0 disables transmission of CEPs and a hexadecimal value of A=FFh indicates repeated transmission of CEPs.
6. The method of claim 1 , wherein Count C is set to a C default value.
7. The method of claim 1 , wherein Count C is set by a user input to the wireless power receiver.
8. The method of claim 1 , wherein Value B is a number between −128 and 0.
9. The method of claim 1 , wherein Value B is set to a B default value.
10. The method of claim 1 , wherein Value B is set by a user input to the wireless power receiver.
11. The method of claim 1 , wherein in a low-power mode the wireless power receiver enables a hardware over-current circuit that generates an OC INT signal when the output current exceeds a current limit.
12. The method of claim 11 , wherein the wireless power receiver operates in low-power mode or in high-power mode according to a user input parameter.
13. The method of claim 11 , wherein the wireless power receiver operates in low power mode or in high power mode according to whether the output current is above or below a transition value.
14. The method of claim 13 , wherein the transition value is set by a user input to the wireless power receiver.
15. A wireless power receiver, comprising:
a rectifier receiving power from a receiver coil and producing a rectified voltage, the receiver coil configured to receive power from a wireless power transmitter;
a power block coupled to receive the rectified voltage and provide an output voltage, the power block further providing an output current IL;
a low-dropout regulator (LDO) limit circuit in the power block;
an amplitude shift key (ASK) modulator coupled to transmit digital data packets to the wireless power transmitter on the power on the receiver coil;
an analog-to-digital converter coupled to provide a digitized output current IL from the output current IL; and
a processor coupled to control the rectifier and the power block, coupled to transmit data packets through the ASK modulator, and coupled to receive the digitized output current IL, the processor executing instructions to, in a high-power mode,
repeatedly compare the digitized output current IL with a current limit value,
while repeatedly comparing, generate an over-current interrupt (OC INT) signal if the digital output current signal is greater than the current limit value and subsequently performing the following steps when the OC INT signal is generated:
transmit Count A number of End Power Transfer (EPT) packets to wireless power transmitter if the OC INT signal is generated,
after Count A EPT packets have been transmitted, stop if it is determined that wireless power transmission has stopped,
transmit Count C number of Control Error Packets (CEPs) with Value B to the wireless power transmitter if it is determined that wireless power transmission has not stopped, and
enable the LDO current limit circuit in a power block of the wireless power receiver if wireless power transmission has not reduced such that the output current IL is below the current limit value.
16. The wireless power receiver of claim 15 , wherein Count A is a value between 0 and hexadecimal FFh, wherein a value A=0 disables transmission of EPT packets and a value A=hexadecimal FFh indicates repeated transmissions of the EPT packets.
17. The wireless power receiver of claim 15 , wherein Count A is set to a A default value.
18. The wireless power receiver of claim 15 , further including an interface coupled to the processor and wherein Count A is set by a user input to the wireless power receiver.
19. The wireless power receiver of claim 15 , wherein Count C is a value between 0 and hexadecimal FFh wherein a value of C=0 disables transmission of CEPs and a value of A=hexadecimal FFh indicates repeated transmission of CEPs.
20. The wireless power receiver of claim 15 , wherein Count C is set to a C default value.
21. The wireless power receiver of claim 15 , further including an interface coupled to the processor and wherein Count C is set by a user input to the wireless power receiver.
22. The wireless power receiver of claim 15 , wherein Value B is a number between −128 and 0.
23. The wireless power receiver of claim 15 , wherein Value B is set to a B default value.
24. The wireless power receiver of claim 15 , further including an interface coupled to the processor and wherein Value B is set by a user input to the wireless power receiver.
25. The wireless power receiver of claim 15 , further including a hardware over-current circuit that receivers the output current IL and provides an over-current interrupt signal if the output current IL exceeds a current limit and wherein the processor executes instructions to
disable the hardware over-current circuit in high-power mode; and
enable the hardware over-current circuit in a low-power mode.
26. The wireless power receiver of claim 25 , further including an interface coupled to the processor and wherein the wireless power receiver operates in low-power mode or in high-power mode according to a user input parameter.
27. The wireless power receiver of claim 25 , wherein the process executes instructions to operate in low power mode or operate in high power mode according to whether the output current IL is above or below a transition value.