Half rate bang-bang phase detector
A half rate bang—bang phase detector for high-speed Analog Clock and Data Recovery (CDR) is disclosed. In some embodiments, the half rate bang—bang phase detector includes a first set of flip flops. Each of the first set of flip flops is configured to receive an input data sampled at each of a four phases of a Voltage Controlled Oscillator (VCO) clock. The half rate bang—bang phase detector includes a first set of logic gates configured to generate a set of four exclusive—OR (XOR) outputs. The half rate bang—bang phase detector includes a second set of flip flops configured to generate a set of clean XOR outputs. The half rate bang—bang phase detector includes a second set of logic gates configured to generate a set of final outputs based on the set of clean XOR outputs.
1. A half rate bang-bang phase detector for high-speed Analog Clock and Data Recovery (CDR), the half rate bang-bang phase detector comprising:
a first set of flip flops, wherein each of the first set of flip flops is configured to receive an input data sampled at each of a four phases of a Voltage Controlled Oscillator (VCO) clock;
a first set of logic gates, wherein each of the first set of logic gates is configured to generate a set of four exclusive-OR (XOR) outputs, and wherein the set of four XOR outputs is generated based on comparison of an output generated by two adjacent intermediate flip flops from the first set of flip flops;
a second set of flip flops, wherein the second set of flip flops is configured to generate a set of clean XOR outputs, and wherein the set of clean XOR outputs is generated based on re-sampling of each of the set of four XOR outputs, wherein the re-sampling XOR outputs by the second set of flip flops is done by CLK180/Clk270, CLK270/Clk0, CLK0/Clk90, CLK90/Clk180 respectively; and
a second set of logic gates, wherein each of the second set of logic gates is configured to generate a set of final outputs based on the set of clean XOR outputs.
2. The half rate bang-bang phase detector of claim 1 , wherein each of the first set of flip flops comprises a first flip flop, a second flip flop, a third flip flop, and a fourth flip flop, and wherein each of the first set of flip flops is a sense amplifier-based flip flop.
3. The half rate bang-bang phase detector of claim 1 , wherein the four phases of the VCO clock comprises CLK0 0 , CLK90 0 , CLK180 0 , and CLK270 0 , and wherein each of the four phases of the VCO clock are at a predetermined phase difference.
4. The half rate bang-bang phase detector of claim 1 , wherein the first set of logic gates comprises four exclusive-OR (XOR) gates, and wherein each of the four exclusive-OR (XOR) gates is configured to:
receive the output generated by each of the two intermediate flip flops from the first set of flip flops; and
compare the output generated by each of the two intermediate flip flops to generate the set of four XOR outputs.
5. The half rate bang-bang phase detector of claim 4 , wherein the set of four XOR outputs comprises UP1_int signal, DN1_int signal, UP2_int signal, and DN2_int signal, and wherein each of the set of four XOR outputs are associated with unwanted quarter pulses occurring periodically at every clock period.
6. The half rate bang-bang phase detector of claim 1 , wherein each of the second set of flip flops is a D flip-flop, and wherein the set of clean XOR outputs generated based on re-sampling of each of the set of four XOR outputs comprises UP1 signal, DN1 signal, UP2 signal, and DN2 signal.
7. The half rate bang-bang phase detector of claim 1 , wherein the second set of logic gates comprises two OR gates in this case, and wherein the set of final outputs includes a final UP signal and a final DN signal.
8. The half rate bang-bang phase detector of claim 7 , wherein each of the set of final outputs is generated by combining two of the set of clean XOR outputs using one of the second set of logic gates.
9. The half rate bang-bang phase detector of claim 8 , wherein each of the set of final outputs generated is sent to a charge pump for adjusting frequency hence the four phases of the VCO clock.
10. A method for capturing phase information during occurrence of data transition at Voltage Controlled Oscillator (VCO), the method comprising:
receiving, by a first set of flip flops of a half rate bang-bang phase detector, an input data sampled at each of a four phases of a VCO clock;
generating, by a first set of logic gates of the half rate bang-bang phase detector, a set of four exclusive-OR (XOR) outputs, wherein the set of four XOR outputs is generated based on comparison of an output generated by two adjacent intermediate flip flops from the first set of flip flops;
generating, by a second set of flip flops of the half rate bang-bang phase detector, a set of clean XOR outputs, wherein the set of clean XOR outputs is generated based on re-sampling of each of the set of four XOR outputs, wherein the re-sampling XOR outputs by the second set of flip flops is done by CLK180/Clk270, CLK270/Clk0, CLK0/Clk90, CLK90/Clk180 respectively; and
producing, by a second set of logic gates of the half rate bang-bang phase detector, a set of final outputs based on the set of clean XOR outputs.
11. The method of claim 10 , wherein each of the first set of flip flops comprises a first flip flop, a second flip flop, a third flip flop, and a fourth flip flop, and wherein each of the first set of flip flops is a sense amplifier-based flip flop.
12. The method of claim 10 , wherein the four phases of the VCO clock comprises CLK0 0 , CLK90 0 , CLK180 0 , and CLK270 0 , and wherein each of the four phases of the VCO clock are at a predetermined phase difference.
13. The method of claim 10 , wherein the first set of logic gates comprises four exclusive-OR (XOR) gates, and wherein each of the four exclusive-OR (XOR) gates is configured to:
receive the output generated by each of the two intermediate flip flops from the first set of flip flops; and
compare the output generated by each of the two intermediate flip flops to generate the set of four XOR outputs.
14. The method of claim 13 , wherein the set of four XOR outputs comprises UP1_int signal, DN1_int signal, UP2_int signal, and DN2_int signal, and wherein each of the set of four XOR outputs are associated with unwanted quarter pulses occurring periodically at every clock period.
15. The method of claim 10 , wherein each of the second set of flip flops is a D flip-flop, and wherein the set of clean XOR outputs generated based on re-sampling of each of the set of four XOR outputs comprises UP1 signal, DN1 signal, UP2 signal, and DN2 signal.
16. The method of claim 10 , wherein the second set of logic gates comprises two OR gates in this case, and wherein the set of final outputs includes a final UP signal and a final DN signal.
17. The method of claim 16 , wherein each of the set of final outputs is generated by combining two of the set of clean XOR outputs using one of the second set of logic gates.
18. The method of claim 17 , wherein each of the set of final outputs generated is sent to a charge pump for adjusting frequency hence the four phases of the VCO clock.