Test generation systems and methods

1. A hardware test suite generator comprising:

a script reader configured to receive a test definition script and parse the test definition script, wherein the test definition script includes first sets of parameters of a design to be tested in combination and one or more second sets of parameters of the design that are forbidden to be tested in combination;

a test generator configured to receive the parsed test definition script from the script reader, the test generator further configured to create a test suite;

a template reader configured to receive a test definition template and parse the test definition template; and

a code generator configured to receive the parsed test definition script from the script reader and receive the parsed test definition template from the template reader and generate code by, for each first set of the first sets, inputting values for the parameters of the design of each first set into the test definition template.

2. The hardware test suite generator of claim 1 , wherein the code generator is further configured to receive the test suite.

3. The hardware test suite generator of claim 1 , wherein the code generator is further configured to generate a test code.

4. The hardware test suite generator of claim 3 , wherein the test code is usable in other verification environments.

5. The hardware test suite generator of claim 3 , wherein the test suite and the test code are communicated to a hardware platform for testing.

6. The hardware test suite generator of claim 5 , wherein the hardware platform includes one of a field-programmable gate array (FPGA), a digital signal processor (DSP), and a microcontroller.

7. The hardware test suite generator of claim 1 , wherein the test definition script can be modified to perform different testing activities.

8. The hardware test suite generator of claim 1 , wherein the test definition script can identify multiple iterations to provide 100% testing coverage such that all combinations of the first sets of parameters are tested and combinations of the second sets of parameters are avoided.

9. The hardware test suite generator of claim 1 , wherein the hardware test suite generator supports tracking during a verification process.

10. The hardware test suite generator of claim 1 , wherein the hardware test suite generator supports an incremental verification process to generate additional test suites that cover additional defined parameter combinations, the additional test suites based only on changes to the test definition script.

11. The hardware test suite generator of claim 1 , wherein the hardware test suite generator defines an n-D space by Base Axis of the test definition script.

12. The hardware test suite generator of claim 1 , wherein creation of the test suite is based on set operations in n-D space.

13. A method comprising:

receiving a test definition script and a test definition template from a user, wherein the test definition script includes first sets of parameters of a design defining base axes of a space for testing and second sets of parameters of the design that are forbidden to be tested in combination;

reading, by a hardware test suite generator, the test definition script and the test definition template;

parsing and composing, by the hardware test suite generator, the test definition script and the test definition template; and

generating, by the hardware test suite generator, a test suite and a test code for each first set of the first sets by inputting values for the parameters of the design of each first set into the test definition template.

14. The method of claim 13 , wherein the test code is usable in other verification environments using additional templates corresponding to the other verification environments.

15. The method of claim 13 , wherein the test suite and the test code are communicated to a hardware platform for testing.

16. The method of claim 15 , wherein the hardware platform includes one of a field-programmable gate array (FPGA), a digital signal processor (DSP), and a microcontroller.

17. The method of claim 13 , wherein the test definition script can be modified to perform different testing activities.

18. The method of claim 13 , wherein the test definition script can identify multiple iterations to provide 100% testing coverage such that all combinations of the first sets of parameters are tested and combinations of the second sets of parameters are avoided.

19. The method of claim 13 , wherein the hardware test suite generator supports an incremental verification process to generate test suites that cover additional defined parameter combinations.